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Commit 2adf7654 authored by Abhimanyu Kapur's avatar Abhimanyu Kapur
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Documentation: msm: Introduce L2 cache clock controller bindings 



Add support for L2 cache clock controller device which is used
to for cache power management.

Change-Id: Ic89b031888225345c738560753e892519544ce31
Signed-off-by: default avatarAbhimanyu Kapur <abhimany@codeaurora.org>
parent 4db402a8
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