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Commit 2a492536 authored by Sahitya Tummala's avatar Sahitya Tummala
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ARM: dts: msm: Reduce SDC1 max clock frequency to 177MHz



The eMMC specification mandates 200MHz as maximum clock frequency
in HS200 mode. On msm8939 due to clock jitter the frequency might
go beyond 200MHz, violating the specification. Reduce the max.
frequency to next available maximum (177MHz).

Change-Id: Ie8791ff7e6305ce97e35e8bbb9f9dd0abf305d59
Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
parent e92aa60f
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