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Commit 1b59aa1d authored by Trilok Soni's avatar Trilok Soni Committed by Stephen Boyd
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msm: vp: Clear APC_PLEVELx register's VREG_PD_EN bit



The current logic in the set_voltage is not clearing
VREG_PD_EN bit, so if this bit is set once then we will see
increase in the one PMIC step size from the given
voltage caller has requested to set.

Change-Id: Id91f0dbdec004bcc111efdcaa08e613240c191b6
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
parent 3bed8af8
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