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Commit 164145b7 authored by Pushkar Joshi's avatar Pushkar Joshi Committed by Stephen Boyd
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ARM: dts: msm: Add CoreSight byte counter interrupt for 8226



The CoreSight block can produce an interrupt on transfer of
programmed number of bytes to ETR-memory. Add device tree
entry to support this feature.

Change-Id: I1d2ff81def7573b1b0ed44dc4c94553594f2a386
Signed-off-by: default avatarPushkar Joshi <pushkarj@codeaurora.org>
parent 0c95f352
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