arm64: errata: add workaround for cortex-a53 erratum #845719

When running a compat (AArch32) userspace on Cortex-A53, a load at EL0
from a virtual address that matches the bottom 32 bits of the virtual
address used by a recent load at (AArch64) EL1 might return incorrect
data.

This patch works around the issue by writing to the contextidr_el1
register on the exception return path when returning to a 32-bit task.
This workaround is patched in at runtime based on the MIDR value of the
processor.

Change-Id: Ic6a838daa6bc7ba1521c65049f14196565eaf545
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Patch-mainline: linux-arm-kernel @ 03/31/2015, 11:08
[rvaswani@codeaurora.org: Resolve merge-conflicts and ignore framework changes]
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>