msm: pil-q6v5-lpass: Enable the axi clock in the secure ops

The LPASS subsystems on some targets contains an SMMU
that also uses the gcc_lpass_q6_axi_clk to talk to DDR.
TZ will no longer control this clock, since the SMMU
driver resides in the non-secure world.

Therefore, enable and disable this clock in the secure
PIL ops.

Change-Id: Ifb0da4c8a374452a4de8ce7f6e58c3a5a3326d5f
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>