clk: qcom: gdsc: Add support to enable a root clock

Due to hardware bug subsystems which has synchronous reset with the
GDSCR the root clock will become active without the software knowledge.
Due to this the source pll needs to be turned on before configuring the
root or a clk_set_rate is issued.

Add a new property qcom,enable-root-clk which will allow sw prepare count
and enable count to be incremented to match the HW state. This will in
turn help in enabling/voting for the pll before the RCGR's new src is
selected. The dummy count will be removed before disabling the GDSCR.

Change-Id: Ife302009b9e672446f7191c4990e61c1f2cd86cd
Signed-off-by: Taniya Das <tdas@codeaurora.org>