msm: clock-alpha-pll: Support new alpha pll type

This new type of pll generates an output frequency of
(L + alpha) * parent_rate. Alpha is expressed as a 40 bit number
instead of being stored as the numerator and denominator of a
fraction.

One of several different pll operating modes will be selected based
on desired frequency.

Change-Id: I09b90fa3f7382dc7b834d0b4e3da10ea1f0ffee1
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>