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Commit 006840a5 authored by Chandan Uddaraju's avatar Chandan Uddaraju
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clk: qcom: mdss: fix debug clock names for DSI PLL on msm8994 



Fix the debug clock names to match with proper clocks for
msm8994. These clocks are part of 20nm PHY PLL configuration.

Change-Id: I709d6df80330702304b91d76ec2cad0a7f494c1e
Signed-off-by: default avatarChandan Uddaraju <chandanu@codeaurora.org>
parent dfc6b80d
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