tg3: Allow DMAs to cross cacheline boundaries

By default, the 5717 (and future chips) break up PCIe DMA packets across
cacheline boundaries.  This isn't necessary on x86.  This patch
selectively loosens the restriction.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>