Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit 8b1c2ba2 authored by San Mehat's avatar San Mehat Committed by Daniel Walker
Browse files

mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays



As it turns out, all sdcc register writes must be delayed by at
least 3 core clock cycles for the writes to take effect. *sigh*

    Also removes the 30us constant delay on clock enable in favor
of a 3 core clock delay.

Signed-off-by: default avatarSan Mehat <san@google.com>
Signed-off-by: default avatarDaniel Walker <dwalker@codeaurora.org>
parent 865c8064
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment