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Commit 46fda15c authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
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ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock



The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.

Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Acked-by: default avatarJaswinder Singh <jaswinder.singh@linaro.org>
[kgene.kim@samsung.com: changed the name of clk for consensus]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 4922972e
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