ASoC: Optimise clock management for WM8915 Speyside

Dynamically enable and disable the FLL on the WM8915, configuring the
system clock to 256fs for 48kHz when the device is active but reverting
to using the input 32.768kHz clock directly at other times to support
features such as jack detection with minimal power consumption.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Liam Girdwood <lrg@ti.com>