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Commit ad54c3dd authored by Nishanth Menon's avatar Nishanth Menon Committed by Kevin Hilman
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ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP



SmartReflex AVS Errorgen module supplies signals to Voltage
Processor. It is suggested that by disabling Errorgen module
before we disable VP, we might be able to ensure lesser
chances of race condition to occur in the system.

Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarJean Pihet <j-pihet@ti.com>
Reviewed-by: default avatarKevin Hilman <khilman@ti.com>
Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
parent 74754cc5
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