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Commit 2d83109b authored by Sarah Sharp's avatar Sarah Sharp Committed by Greg Kroah-Hartman
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USB: xhci: Correct Event Handler Busy flag usage. 



The Event Handler Busy bit in the event ring dequeue pointer is write 1 to
clear.  Fix the interrupt service routine to clear that bit after the
event handler has run.

xhci_set_hc_event_deq() is designed to update the event ring dequeue pointer
without changing any of the four reserved bits in the lower nibble.  The event
handler busy (EHB) bit is write one to clear, so the new value must always
contain a zero in that bit in order to preserve the EHB value.

Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 62889610

drivers/usb/host/xhci-hcd.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -249,9 +249,9 @@ static void xhci_work(struct xhci_hcd *xhci) 
	/* FIXME this should be a delayed service routine that clears the EHB */

	/* FIXME this should be a delayed service routine that clears the EHB */

	xhci_handle_event(xhci);

	xhci_handle_event(xhci);





	/* Clear the event handler busy flag; the event ring should be empty. */

	/* Clear the event handler busy flag (RW1C); the event ring should be empty. */

	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);

	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);

	xhci_write_64(xhci, temp_64 & ~ERST_EHB, &xhci->ir_set->erst_dequeue);

	xhci_write_64(xhci, temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue);

	/* Flush posted writes -- FIXME is this necessary? */

	/* Flush posted writes -- FIXME is this necessary? */

	xhci_readl(xhci, &xhci->ir_set->irq_pending);

	xhci_readl(xhci, &xhci->ir_set->irq_pending);

}

}

drivers/usb/host/xhci-ring.c

+5 −1
Original line number Original line Diff line number Diff line
@@ -248,8 +248,12 @@ void xhci_set_hc_event_deq(struct xhci_hcd *xhci) 
	/* Update HC event ring dequeue pointer */

	/* Update HC event ring dequeue pointer */

	temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);

	temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);

	temp &= ERST_PTR_MASK;

	temp &= ERST_PTR_MASK;

	/* Don't clear the EHB bit (which is RW1C) because

	 * there might be more events to service.

	 */

	temp &= ~ERST_EHB;

	if (!in_interrupt())

	if (!in_interrupt())

		xhci_dbg(xhci, "// Write event ring dequeue pointer\n");

		xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");

	xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,

	xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,

			&xhci->ir_set->erst_dequeue);

			&xhci->ir_set->erst_dequeue);

}

}