Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit 22bd1f7e authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: dt: tegra seaboard: fix I2C2 SCL rate



This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent b46b0b54
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment