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Commit effca0e8 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: npu: Support different sub block io spaces"

parents dad27a69 6a106faf

arch/arm64/boot/dts/qcom/sdmmagpie-npu.dtsi

+67 −65
Original line number Diff line number Diff line
@@ -13,9 +13,11 @@ 
&soc {

	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		reg = <0x9800000 0x800000>,

		reg = <0x9900000 0x40000>,

			<0x9900000 0x10000>,

			<0x9960200 0x600>,

			<0x780000 0x7000>;

		reg-names = "npu_base", "qfprom_physical";

		reg-names = "tcm", "core", "bwmon", "qfprom_physical";

		interrupts = <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 587 IRQ_TYPE_EDGE_RISING>;
@@ -24,42 +26,42 @@ 
		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;



		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>,

		clocks = <&clock_aop QDSS_CLK>,

			<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

			<&clock_npucc NPU_CC_BTO_CORE_CLK>,

			<&clock_npucc NPU_CC_BWMON_CLK>,

			<&clock_npucc NPU_CC_CAL_DP_CLK>,

			<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,

			<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

			<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

			<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

			<&clock_npucc NPU_CC_NPU_CPC_CLK>,

			<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

			<&clock_npucc NPU_CC_PERF_CNT_CLK>,

			<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

			<&clock_npucc NPU_CC_SLEEP_CLK>,

			<&clock_aop QDSS_CLK>;

		clock-names = "cal_dp_clk",

			"xo_clk",

			<&clock_npucc NPU_CC_BWMON_CLK>,

			<&clock_npucc NPU_CC_PERF_CNT_CLK>,

			<&clock_npucc NPU_CC_BTO_CORE_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>;

		clock-names = "qdss_clk",

			"armwic_core_clk",

			"bto_core_clk",

			"bwmon_clk",

			"cal_dp_clk",

			"cal_dp_cdc_clk",

			"comp_noc_axi_clk",

			"conf_noc_ahb_clk",

			"npu_core_apb_clk",

			"npu_core_atb_clk",

			"comp_noc_axi_clk",

			"npu_core_clk",

			"npu_core_cti_clk",

			"npu_core_apb_clk",

			"npu_core_atb_clk",

			"npu_cpc_clk",

			"npu_cpc_timer_clk",

			"perf_cnt_clk",

			"qtimer_core_clk",

			"sleep_clk",

			"qdss_clk";

			"bwmon_clk",

			"perf_cnt_clk",

			"bto_core_clk",

			"xo_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";
@@ -77,112 +79,112 @@ 
			qcom,npu-pwrlevel@0 {

				reg = <0>;

				vreg = <1>;

				clk-freq = <300000000

					19200000

				clk-freq = <0

					100000000

					19200000

					19200000

					300000000

					150000000

					300000000

					30000000

					19200000

					60000000

					150000000

					100000000

					37500000

					19200000

					60000000

					100000000

					19200000

					300000000

					19200000

					0

					0>;

					19200000

					300000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				vreg = <2>;

				clk-freq = <400000000

					19200000

				clk-freq = <0

					150000000

					19200000

					19200000

					400000000

					200000000

					400000000

					37500000

					19200000

					120000000

					200000000

					150000000

					75000000

					19200000

					120000000

					150000000

					19200000

					400000000

					19200000

					0

					0>;

					19200000

					400000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				vreg = <3>;

				clk-freq = <466500000

					19200000

				clk-freq = <0

					200000000

					19200000

					19200000

					466500000

					300000000

					466500000

					37500000

					19200000

					120000000

					300000000

					200000000

					75000000

					19200000

					120000000

					200000000

					19200000

					466500000

					19200000

					0

					0>;

					19200000

					466500000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				vreg = <4>;

				clk-freq = <600000000

					19200000

				clk-freq = <0

					300000000

					19200000

					19200000

					600000000

					403000000

					600000000

					75000000

					19200000

					240000000

					403000000

					300000000

					150000000

					19200000

					240000000

					300000000

					19200000

					600000000

					19200000

					0

					0>;

					19200000

					600000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				vreg = <6>;

				clk-freq = <700000000

					19200000

				clk-freq = <0

					400000000

					19200000

					19200000

					700000000

					533000000

					700000000

					75000000

					19200000

					300000000

					533000000

					400000000

					150000000

					19200000

					300000000

					400000000

					19200000

					700000000

					19200000

					0

					0>;

					19200000

					700000000

					19200000

					19200000>;

			};

		};

	};

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+126 −124
Original line number Diff line number Diff line
@@ -14,8 +14,10 @@ 
	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		status = "ok";

		reg = <0x9800000 0x800000>;

		reg-names = "npu_base";

		reg = <0x9800000 0x40000>,

			<0x9900000 0x10000>,

			<0x9960200 0x600>;

		reg-names = "tcm", "core", "bwmon";

		interrupts = <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
@@ -23,46 +25,46 @@ 
		iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;

		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;

		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

				<&clock_npucc NPU_CC_XO_CLK>,

		clocks = <&clock_aop QDSS_CLK>,

				<&clock_gcc GCC_NPU_AT_CLK>,

				<&clock_gcc GCC_NPU_TRIG_CLK>,

				<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,

				<&clock_npucc NPU_CC_BWMON_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,

				<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

				<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

				<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

				<&clock_npucc NPU_CC_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

				<&clock_npucc NPU_CC_SLEEP_CLK>,

				<&clock_gcc GCC_NPU_AT_CLK>,

				<&clock_gcc GCC_NPU_TRIG_CLK>,

				<&clock_aop QDSS_CLK>;

		clock-names = "cal_dp_clk",

				"xo_clk",

				<&clock_npucc NPU_CC_BWMON_CLK>,

				<&clock_npucc NPU_CC_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,

				<&clock_npucc NPU_CC_XO_CLK>;

		clock-names = "qdss_clk",

				"at_clk",

				"trig_clk",

				"armwic_core_clk",

				"bto_core_clk",

				"bwmon_clk",

				"cal_dp_clk",

				"cal_dp_cdc_clk",

				"comp_noc_axi_clk",

				"conf_noc_ahb_clk",

				"npu_core_apb_clk",

				"npu_core_atb_clk",

				"comp_noc_axi_clk",

				"npu_core_clk",

				"npu_core_cti_clk",

				"npu_core_apb_clk",

				"npu_core_atb_clk",

				"npu_cpc_clk",

				"npu_cpc_timer_clk",

				"perf_cnt_clk",

				"qtimer_core_clk",

				"sleep_clk",

				"at_clk",

				"trig_clk",

				"qdss_clk";

				"bwmon_clk",

				"perf_cnt_clk",

				"bto_core_clk",

				"xo_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";
@@ -80,122 +82,122 @@ 
			qcom,npu-pwrlevel@0 {

				reg = <0>;

				vreg = <1>;

				clk-freq = <300000000

						19200000

				clk-freq = <0

					0

					0

					100000000

						19200000

						19200000

					300000000

						150000000

						19200000

					300000000

					19200000

						60000000

					150000000

					100000000

					37500000

					19200000

					60000000

					100000000

					19200000

						300000000

					19200000

					0

						0

						0

						0>;

					19200000

					300000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				vreg = <2>;

				clk-freq = <350000000

						19200000

				clk-freq = <0

					0

					0

					150000000

						19200000

						19200000

					350000000

						200000000

					350000000

					37500000

						19200000

						120000000

					200000000

					150000000

					75000000

					19200000

					120000000

					150000000

					19200000

						350000000

					19200000

					0

						0

						0

						0>;

					19200000

					350000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				vreg = <3>;

				clk-freq = <400000000

						19200000

				clk-freq = <0

					0

					0

					200000000

						19200000

						19200000

					400000000

						300000000

					400000000

					37500000

						19200000

						120000000

					300000000

					200000000

					75000000

					19200000

					120000000

					200000000

					19200000

						400000000

					19200000

					0

						0

						0

						0>;

					19200000

					400000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				vreg = <4>;

				clk-freq = <600000000

						19200000

				clk-freq = <0

					0

					0

					300000000

						19200000

						19200000

					600000000

						403000000

					600000000

					75000000

						19200000

						240000000

					403000000

					300000000

					150000000

					19200000

					240000000

					300000000

					19200000

						600000000

					19200000

					0

						0

						0

						0>;

					19200000

					600000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				vreg = <6>;

				clk-freq = <715000000

						19200000

				clk-freq = <0

					0

					0

					350000000

						19200000

						19200000

					715000000

						533000000

					715000000

					75000000

						19200000

						240000000

					533000000

					350000000

					150000000

					19200000

					240000000

					350000000

					19200000

						715000000

					19200000

					0

						0

						0

						0>;

					19200000

					715000000

					19200000

					19200000>;

			};

		};

	};

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+120 −120
Original line number Diff line number Diff line
@@ -709,146 +709,146 @@ 
		qcom,npu-pwrlevel@0 {

			reg = <0>;

			vreg = <1>;

			clk-freq = <300000000

					19200000

			clk-freq = <0

				0

				0

				100000000

					19200000

					19200000

				300000000

					150000000

					19200000

				300000000

				19200000

					60000000

				150000000

				100000000

				37500000

				19200000

				60000000

				100000000

				19200000

					300000000

				19200000

				0

					0

					0

					0>;

				19200000

				300000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@1 {

			reg = <1>;

			vreg = <2>;

			clk-freq = <400000000

					19200000

			clk-freq = <0

				0

				0

				150000000

					19200000

					19200000

				400000000

					200000000

				400000000

				37500000

					19200000

					120000000

				200000000

				150000000

				75000000

				19200000

				120000000

				150000000

				19200000

					400000000

				19200000

				0

					0

					0

					0>;

				19200000

				400000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@2 {

			reg = <2>;

			vreg = <3>;

			clk-freq = <487000000

					19200000

			clk-freq = <0

				0

				0

				200000000

					19200000

					19200000

				487000000

					300000000

				487000000

				37500000

					19200000

					240000000

				300000000

				200000000

				150000000

				19200000

				240000000

				200000000

				19200000

					487000000

				19200000

				0

					0

					0

					0>;

				19200000

				487000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@3 {

			reg = <3>;

			vreg = <4>;

			clk-freq = <652000000

					19200000

			clk-freq = <0

				0

				0

				300000000

					19200000

					19200000

				652000000

					403000000

				652000000

				75000000

					19200000

					240000000

				403000000

				300000000

				150000000

				19200000

				240000000

				300000000

				19200000

					652000000

				19200000

				0

					0

					0

					0>;

				19200000

				652000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@4 {

			reg = <4>;

			vreg = <6>;

			clk-freq = <811000000

					19200000

			clk-freq = <0

				0

				0

				400000000

					19200000

					19200000

				811000000

					533000000

				811000000

				75000000

					19200000

					300000000

				533000000

				400000000

				150000000

				19200000

				300000000

				400000000

				19200000

					811000000

				19200000

				0

					0

					0

					0>;

				19200000

				811000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@5 {

			reg = <5>;

			vreg = <7>;

			clk-freq = <908000000

					19200000

			clk-freq = <0

				0

				0

				400000000

					19200000

					19200000

				908000000

					533000000

				908000000

				75000000

					19200000

					300000000

				533000000

				400000000

				150000000

				19200000

				300000000

				400000000

				19200000

					908000000

				19200000

				0

					0

					0

					0>;

				19200000

				908000000

				19200000

				19200000>;

		};

	};

};

drivers/media/platform/msm/npu/npu_common.h

+3 −1
Original line number Diff line number Diff line
@@ -208,7 +208,9 @@ struct npu_device { 
	struct class *class;

	struct device *device;



	struct npu_io_data npu_io;

	struct npu_io_data core_io;

	struct npu_io_data tcm_io;

	struct npu_io_data bwmon_io;

	struct npu_io_data qfprom_io;



	uint32_t core_clk_num;

drivers/media/platform/msm/npu/npu_dbg.c

+0 −305
Original line number Diff line number Diff line
@@ -22,275 +22,6 @@ 
#include "npu_hw_access.h"

#include "npu_mgr.h"



/* -------------------------------------------------------------------------

 * File Scope Variables

 * -------------------------------------------------------------------------

 */

static const uint32_t debug_cal_reg_list[] = {

	CAL_DP_DMA_WR_RLD_CMD_0,

	CAL_DP_DMA_RD_RLD_CMD_0,

	CAL_DP_DMA_RD_RLD_CMD_1,

	CAL_DP_DMA_RD_RLD_CMD_2,

	CAL_DP_DMA_RD_RLD_CMD_3,

	CAL_DP_DMA_LOC_RLD_CMD_0,

	CAL_DP_DMA_BUS_CFG,

	CAL_DP_DMA_BUS_OT_CFG,

	CAL_DP_DMA_WR_CFG_0,

	CAL_DP_DMA_WR_NUM_CMD_IT_0,

	CAL_DP_DMA_WR_START_ADDR_0,

	CAL_DP_DMA_WR_MAX_ADDR_0,

	CAL_DP_DMA_WR_STRIDE_DIM0_0,

	CAL_DP_DMA_WR_STRIDE_DIM1_0,

	CAL_DP_DMA_WR_STRIDE_DIM2_0,

	CAL_DP_DMA_WR_ROW_INCR_0,

	CAL_DP_DMA_WR_DIM0_XSIZE_0,

	CAL_DP_DMA_WR_DIM0_INCR_0,

	CAL_DP_DMA_WR_DIM0_NUM_BLK_0,

	CAL_DP_DMA_WR_DIM1_XSIZE_0,

	CAL_DP_DMA_WR_DIM1_YSIZE_0,

	CAL_DP_DMA_WR_DIM2_XSIZE_0,

	CAL_DP_DMA_WR_DIM2_YSIZE_0,

	CAL_DP_DMA_WR_CLIENT_BLK_SIZE_CFG_0,

	CAL_DP_DMA_WR_CLIENT_ADDR_CFG_0,

	CAL_DP_DMA_WR_CLIENT_BUFF_CFG_0,

	CAL_DP_DMA_WR_MMU_CFG_0,

	CAL_DP_DMA_RD_CFG_0,

	CAL_DP_DMA_RD_NUM_CMD_IT_0,

	CAL_DP_DMA_RD_START_ADDR_0,

	CAL_DP_DMA_RD_START_ADDR1_0,

	CAL_DP_DMA_RD_END_ADDR0_0,

	CAL_DP_DMA_RD_MAX_ADDR_0,

	CAL_DP_DMA_RD_MAX_ADDR1_0,

	CAL_DP_DMA_RD_STRIDE_DIM0_0,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_0,

	CAL_DP_DMA_RD_STRIDE_DIM1_0,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_0,

	CAL_DP_DMA_RD_STRIDE_DIM2_0,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_0,

	CAL_DP_DMA_RD_ROW_INCR_0,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_0,

	CAL_DP_DMA_RD_DIM0_INCR_0,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_0,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_0,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_0,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_0,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_0,

	CAL_DP_DMA_RD_DIM0_PAD_L_0,

	CAL_DP_DMA_RD_DIM0_PAD_R_0,

	CAL_DP_DMA_RD_PAD_TB_0,

	CAL_DP_DMA_RD_DIM0_CROP_0,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_0,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_0,

	CAL_DP_DMA_RD_MMU_CFG_0,

	CAL_DP_DMA_RD_PAD_VALUE_0,

	CAL_DP_DMA_RD_CFG_1,

	CAL_DP_DMA_RD_NUM_CMD_IT_1,

	CAL_DP_DMA_RD_START_ADDR_1,

	CAL_DP_DMA_RD_START_ADDR1_1,

	CAL_DP_DMA_RD_END_ADDR0_1,

	CAL_DP_DMA_RD_MAX_ADDR_1,

	CAL_DP_DMA_RD_MAX_ADDR1_1,

	CAL_DP_DMA_RD_STRIDE_DIM0_1,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_1,

	CAL_DP_DMA_RD_STRIDE_DIM1_1,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_1,

	CAL_DP_DMA_RD_STRIDE_DIM2_1,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_1,

	CAL_DP_DMA_RD_ROW_INCR_1,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_1,

	CAL_DP_DMA_RD_DIM0_INCR_1,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_1,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_1,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_1,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_1,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_1,

	CAL_DP_DMA_RD_DIM0_PAD_L_1,

	CAL_DP_DMA_RD_DIM0_PAD_R_1,

	CAL_DP_DMA_RD_PAD_TB_1,

	CAL_DP_DMA_RD_DIM0_CROP_1,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_1,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_1,

	CAL_DP_DMA_RD_MMU_CFG_1,

	CAL_DP_DMA_RD_PAD_VALUE_1,

	CAL_DP_DMA_RD_CFG_2,

	CAL_DP_DMA_RD_NUM_CMD_IT_2,

	CAL_DP_DMA_RD_START_ADDR_2,

	CAL_DP_DMA_RD_START_ADDR1_2,

	CAL_DP_DMA_RD_END_ADDR0_2,

	CAL_DP_DMA_RD_MAX_ADDR_2,

	CAL_DP_DMA_RD_MAX_ADDR1_2,

	CAL_DP_DMA_RD_STRIDE_DIM0_2,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_2,

	CAL_DP_DMA_RD_STRIDE_DIM1_2,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_2,

	CAL_DP_DMA_RD_STRIDE_DIM2_2,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_2,

	CAL_DP_DMA_RD_ROW_INCR_2,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_2,

	CAL_DP_DMA_RD_DIM0_INCR_2,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_2,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_2,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_2,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_2,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_2,

	CAL_DP_DMA_RD_DIM0_PAD_L_2,

	CAL_DP_DMA_RD_DIM0_PAD_R_2,

	CAL_DP_DMA_RD_PAD_TB_2,

	CAL_DP_DMA_RD_DIM0_CROP_2,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_2,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_2,

	CAL_DP_DMA_RD_MMU_CFG_2,

	CAL_DP_DMA_RD_PAD_VALUE_2,

	CAL_DP_DMA_RD_CFG_3,

	CAL_DP_DMA_RD_NUM_CMD_IT_3,

	CAL_DP_DMA_RD_START_ADDR_3,

	CAL_DP_DMA_RD_START_ADDR1_3,

	CAL_DP_DMA_RD_END_ADDR0_3,

	CAL_DP_DMA_RD_MAX_ADDR_3,

	CAL_DP_DMA_RD_MAX_ADDR1_3,

	CAL_DP_DMA_RD_STRIDE_DIM0_3,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_3,

	CAL_DP_DMA_RD_STRIDE_DIM1_3,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_3,

	CAL_DP_DMA_RD_STRIDE_DIM2_3,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_3,

	CAL_DP_DMA_RD_ROW_INCR_3,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_3,

	CAL_DP_DMA_RD_DIM0_INCR_3,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_3,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_3,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_3,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_3,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_3,

	CAL_DP_DMA_RD_DIM0_PAD_L_3,

	CAL_DP_DMA_RD_DIM0_PAD_R_3,

	CAL_DP_DMA_RD_PAD_TB_3,

	CAL_DP_DMA_RD_DIM0_CROP_3,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_3,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_3,

	CAL_DP_DMA_RD_MMU_CFG_3,

	CAL_DP_DMA_RD_PAD_VALUE_3,

	CAL_DP_DMA_LOC_SRC_ADDR_0,

	CAL_DP_DMA_LOC_DEST_ADDR_0,

	CAL_DP_DMA_LOC_DATA_SIZE_0,

	CAL_DP_DMA_WR_ERR_STATUS_0,

	CAL_DP_DMA_WR_MAX_P_CNT_0,

	CAL_DP_DMA_WR_STATUS_0_0,

	CAL_DP_DMA_WR_STATUS_0_1,

	CAL_DP_DMA_WR_STATUS_0_2,

	CAL_DP_DMA_WR_STATUS_0_3,

	CAL_DP_DMA_RD_ERR_STATUS_0,

	CAL_DP_DMA_RD_MAX_P_CNT_0,

	CAL_DP_DMA_RD_STATUS_0_0,

	CAL_DP_DMA_RD_STATUS_0_1,

	CAL_DP_DMA_RD_STATUS_0_2,

	CAL_DP_DMA_RD_STATUS_0_3,

	CAL_DP_DMA_RD_STATUS_0_4,

	CAL_DP_DMA_RD_ERR_STATUS_1,

	CAL_DP_DMA_RD_MAX_P_CNT_1,

	CAL_DP_DMA_RD_STATUS_1_0,

	CAL_DP_DMA_RD_STATUS_1_1,

	CAL_DP_DMA_RD_STATUS_1_2,

	CAL_DP_DMA_RD_STATUS_1_3,

	CAL_DP_DMA_RD_STATUS_1_4,

	CAL_DP_DMA_RD_ERR_STATUS_2,

	CAL_DP_DMA_RD_MAX_P_CNT_2,

	CAL_DP_DMA_RD_STATUS_2_0,

	CAL_DP_DMA_RD_STATUS_2_1,

	CAL_DP_DMA_RD_STATUS_2_2,

	CAL_DP_DMA_RD_STATUS_2_3,

	CAL_DP_DMA_RD_STATUS_2_4,

	CAL_DP_DMA_RD_ERR_STATUS_3,

	CAL_DP_DMA_RD_MAX_P_CNT_3,

	CAL_DP_DMA_RD_STATUS_3_0,

	CAL_DP_DMA_RD_STATUS_3_1,

	CAL_DP_DMA_RD_STATUS_3_2,

	CAL_DP_DMA_RD_STATUS_3_3,

	CAL_DP_DMA_LOC_ERR_STATUS_0,

	CAL_DP_DMA_LOC_STATUS_0_0,

	CAL_DP_DMA_LOC_STATUS_0_1,

	CAL_DP_DMA_LOC_STATUS_0_2,

	CAL_DP_DMA_LOC_STATUS_0_3,

	CAL_DP_CALDMA_ADAPT_STATUS_0_0,

	CAL_DP_CALDMA_ADAPT_STATUS_0_1,

	CAL_DP_SDMA_WR_STATUS_0_0,

	CAL_DP_SDMA_WR_STATUS_0_1,

	CAL_DP_SDMA_WR_STATUS_0_2,

	CAL_DP_SDMA_WR_STATUS_0_3,

	CAL_DP_SDMA_WR_STATUS_0_4,

	CAL_DP_SDMA_WR_STATUS_0_5,

	CAL_DP_SDMA_WR_STATUS_0_6,

	CAL_DP_SDMA_WR_STATUS_0_7,

	CAL_DP_SDMA_WR_STATUS_0_8,

	CAL_DP_SDMA_RD_STATUS_0_0,

	CAL_DP_SDMA_RD_STATUS_0_1,

	CAL_DP_SDMA_RD_STATUS_0_2,

	CAL_DP_SDMA_RD_STATUS_0_3,

	CAL_DP_SDMA_RD_STATUS_0_4,

	CAL_DP_SDMA_RD_STATUS_0_5,

	CAL_DP_SDMA_RD_STATUS_0_6,

	CAL_DP_SDMA_RD_STATUS_0_7,

	CAL_DP_SDMA_RD_STATUS_0_8,

	CAL_DP_SDMA_RD_STATUS_0_9,

	CAL_DP_SDMA_RD_STATUS_0_10,

	CAL_DP_TCM_SET_CMD,

	CAL_DP_TCM_RESET_CMD,

	CAL_DP_DTSWC_INT_CLR,

	CAL_DP_TCM_INT_CLR,

	CAL_DP_DTSWC_INT_SET,

	CAL_DP_TCM_INT_SET,

	CAL_DP_WD_RSS_CMD,

	CAL_DP_RESET_CMD,

	CAL_DP_PERF_CNT_CMD,

	CAL_DP_DBUF_TRANSFER_CMD,

	CAL_DP_CAL_EN_CTRL,

	CAL_DP_EN_INT_CTRL,

	CAL_DP_EN_TCM_INT_CTRL,

	CAL_DP_TCM_VAL_CTRL,

	CAL_DP_WD_COUNT_LO,

	CAL_DP_WD_COUNT_HI,

	CAL_DP_RSS_SEL_CTRL,

	CAL_DP_CAL_CFG_W0,

	CAL_DP_CAL_CFG_W1,

	CAL_DP_CAL_CFG_W2,

	CAL_DP_CAL_CFG_W3,

	CAL_DP_PERF_CNT_START_SEL,

	CAL_DP_PERF_CNT_STOP_SEL,

	CAL_DP_PERF_CNT_EVENT_SEL,

	CAL_DP_DBUF_RD_SEL,

	CAL_DP_LM_CTRL,

	CAL_DP_LM_LOOK_AHEAD,

	CAL_DP_LM_CUB_TIMER,

	CAL_DP_SIGB_STATUS,

	CAL_DP_CAL_EN_WD_RSS_STATUS,

	CAL_DP_EN_TCM_FLAGS_STATUS,

	CAL_DP_VERSION_STATUS,

	CAL_DP_CFG_STATUS,

	CAL_DP_CUB_SAT_DTCT_STATUS,

	CAL_DP_AHB_ERR_ADDR_STATUS,

	CAL_DP_WD_STATUS_LO,

	CAL_DP_WD_STATUS_HI,

	CAL_DP_DTSWC_INT_STATUS,

	CAL_DP_DTSWC_TCM_INT_STATUS,

	CAL_DP_DTSWC_UM_INT_STATUS,

	CAL_DP_DTSWC_TCM_UM_INT_STATUS,

	CAL_DP_RSS_STATUS,

	CAL_DP_RSS_STATUS_1,

	CAL_DP_RSS_STATUS_2,

	CAL_DP_RSS_STATUS_3,

	CAL_DP_RSS_STATUS_4,

	CAL_DP_RSS_STATUS_5,

	CAL_DP_RSS_STATUS_6,

	CAL_DP_RSS_STATUS_7,

	CAL_DP_PERF_CNT0,

	CAL_DP_PERF_CNT1,

	CAL_DP_PERF_CNT2,

	CAL_DP_PERF_CNT3,

	CAL_DP_FINAL_MIN,

	CAL_DP_FINAL_MAX,

	CAL_DP_LM_STATUS

};



/* -------------------------------------------------------------------------

 * Function Definitions - Debug

 * -------------------------------------------------------------------------
@@ -306,39 +37,3 @@ void npu_dump_debug_timeout_stats(struct npu_device *npu_dev) 
	reg_val = REGR(npu_dev, REG_NPU_FW_DEBUG_DATA);

	pr_info("fw jobs aco parser debug = %d\n", reg_val);

}
 


void npu_dump_cal_state(struct npu_device *npu_dev)

{

	uint32_t reg_val;

	uint32_t i;



	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_START_ADDR_0);

	pr_info("DMA RD 0 Addr: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_WR_START_ADDR_0);

	pr_info("DMA WR Addr: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_START_ADDR_1);

	pr_info("DMA RD 1 Addr: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_START_ADDR_2);

	pr_info("DMA RD 2 Addr: 0x%x\n", reg_val);



	/* mask irq status reg */

	reg_val = REGR(npu_dev, CAL_DP_DTSWC_INT_STATUS);

	pr_info("Masked ISR Status: 0x%x\n", reg_val);



	/* unmasked mask irq status reg */

	reg_val = REGR(npu_dev, CAL_DP_DTSWC_UM_INT_STATUS);

	pr_info("UnMasked ISR Status: 0x%x\n", reg_val);



	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_ERR_STATUS_0);

	pr_info("rd err 0 Status: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_ERR_STATUS_1);

	pr_info("rd err 1 Status: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_ERR_STATUS_2);

	pr_info("rd err 2 Status: 0x%x\n", reg_val);



	for (i = 0; i < sizeof(debug_cal_reg_list) / sizeof(uint32_t); i++) {

		reg_val = REGR(npu_dev, debug_cal_reg_list[i]);

		pr_info("Reg = 0x%x Val = 0x%x\n", debug_cal_reg_list[i],

			reg_val);

	}

}