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Commit 6a106faf authored by Jilai Wang's avatar Jilai Wang
Browse files

msm: npu: Support different sub block io spaces 



This change is to break npu_base io space into different io spaces
based on functionality and access them using different functions.

Change-Id: Ibe94c910edbf44072e3f407425076a3d90e52cd8
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 8010bb0b

drivers/media/platform/msm/npu/npu_common.h

+3 −1
Original line number Diff line number Diff line
@@ -208,7 +208,9 @@ struct npu_device { 
	struct class *class;

	struct device *device;



	struct npu_io_data npu_io;

	struct npu_io_data core_io;

	struct npu_io_data tcm_io;

	struct npu_io_data bwmon_io;

	struct npu_io_data qfprom_io;



	uint32_t core_clk_num;

drivers/media/platform/msm/npu/npu_dbg.c

+0 −305
Original line number Diff line number Diff line
@@ -22,275 +22,6 @@ 
#include "npu_hw_access.h"

#include "npu_mgr.h"



/* -------------------------------------------------------------------------

 * File Scope Variables

 * -------------------------------------------------------------------------

 */

static const uint32_t debug_cal_reg_list[] = {

	CAL_DP_DMA_WR_RLD_CMD_0,

	CAL_DP_DMA_RD_RLD_CMD_0,

	CAL_DP_DMA_RD_RLD_CMD_1,

	CAL_DP_DMA_RD_RLD_CMD_2,

	CAL_DP_DMA_RD_RLD_CMD_3,

	CAL_DP_DMA_LOC_RLD_CMD_0,

	CAL_DP_DMA_BUS_CFG,

	CAL_DP_DMA_BUS_OT_CFG,

	CAL_DP_DMA_WR_CFG_0,

	CAL_DP_DMA_WR_NUM_CMD_IT_0,

	CAL_DP_DMA_WR_START_ADDR_0,

	CAL_DP_DMA_WR_MAX_ADDR_0,

	CAL_DP_DMA_WR_STRIDE_DIM0_0,

	CAL_DP_DMA_WR_STRIDE_DIM1_0,

	CAL_DP_DMA_WR_STRIDE_DIM2_0,

	CAL_DP_DMA_WR_ROW_INCR_0,

	CAL_DP_DMA_WR_DIM0_XSIZE_0,

	CAL_DP_DMA_WR_DIM0_INCR_0,

	CAL_DP_DMA_WR_DIM0_NUM_BLK_0,

	CAL_DP_DMA_WR_DIM1_XSIZE_0,

	CAL_DP_DMA_WR_DIM1_YSIZE_0,

	CAL_DP_DMA_WR_DIM2_XSIZE_0,

	CAL_DP_DMA_WR_DIM2_YSIZE_0,

	CAL_DP_DMA_WR_CLIENT_BLK_SIZE_CFG_0,

	CAL_DP_DMA_WR_CLIENT_ADDR_CFG_0,

	CAL_DP_DMA_WR_CLIENT_BUFF_CFG_0,

	CAL_DP_DMA_WR_MMU_CFG_0,

	CAL_DP_DMA_RD_CFG_0,

	CAL_DP_DMA_RD_NUM_CMD_IT_0,

	CAL_DP_DMA_RD_START_ADDR_0,

	CAL_DP_DMA_RD_START_ADDR1_0,

	CAL_DP_DMA_RD_END_ADDR0_0,

	CAL_DP_DMA_RD_MAX_ADDR_0,

	CAL_DP_DMA_RD_MAX_ADDR1_0,

	CAL_DP_DMA_RD_STRIDE_DIM0_0,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_0,

	CAL_DP_DMA_RD_STRIDE_DIM1_0,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_0,

	CAL_DP_DMA_RD_STRIDE_DIM2_0,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_0,

	CAL_DP_DMA_RD_ROW_INCR_0,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_0,

	CAL_DP_DMA_RD_DIM0_INCR_0,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_0,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_0,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_0,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_0,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_0,

	CAL_DP_DMA_RD_DIM0_PAD_L_0,

	CAL_DP_DMA_RD_DIM0_PAD_R_0,

	CAL_DP_DMA_RD_PAD_TB_0,

	CAL_DP_DMA_RD_DIM0_CROP_0,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_0,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_0,

	CAL_DP_DMA_RD_MMU_CFG_0,

	CAL_DP_DMA_RD_PAD_VALUE_0,

	CAL_DP_DMA_RD_CFG_1,

	CAL_DP_DMA_RD_NUM_CMD_IT_1,

	CAL_DP_DMA_RD_START_ADDR_1,

	CAL_DP_DMA_RD_START_ADDR1_1,

	CAL_DP_DMA_RD_END_ADDR0_1,

	CAL_DP_DMA_RD_MAX_ADDR_1,

	CAL_DP_DMA_RD_MAX_ADDR1_1,

	CAL_DP_DMA_RD_STRIDE_DIM0_1,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_1,

	CAL_DP_DMA_RD_STRIDE_DIM1_1,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_1,

	CAL_DP_DMA_RD_STRIDE_DIM2_1,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_1,

	CAL_DP_DMA_RD_ROW_INCR_1,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_1,

	CAL_DP_DMA_RD_DIM0_INCR_1,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_1,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_1,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_1,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_1,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_1,

	CAL_DP_DMA_RD_DIM0_PAD_L_1,

	CAL_DP_DMA_RD_DIM0_PAD_R_1,

	CAL_DP_DMA_RD_PAD_TB_1,

	CAL_DP_DMA_RD_DIM0_CROP_1,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_1,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_1,

	CAL_DP_DMA_RD_MMU_CFG_1,

	CAL_DP_DMA_RD_PAD_VALUE_1,

	CAL_DP_DMA_RD_CFG_2,

	CAL_DP_DMA_RD_NUM_CMD_IT_2,

	CAL_DP_DMA_RD_START_ADDR_2,

	CAL_DP_DMA_RD_START_ADDR1_2,

	CAL_DP_DMA_RD_END_ADDR0_2,

	CAL_DP_DMA_RD_MAX_ADDR_2,

	CAL_DP_DMA_RD_MAX_ADDR1_2,

	CAL_DP_DMA_RD_STRIDE_DIM0_2,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_2,

	CAL_DP_DMA_RD_STRIDE_DIM1_2,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_2,

	CAL_DP_DMA_RD_STRIDE_DIM2_2,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_2,

	CAL_DP_DMA_RD_ROW_INCR_2,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_2,

	CAL_DP_DMA_RD_DIM0_INCR_2,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_2,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_2,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_2,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_2,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_2,

	CAL_DP_DMA_RD_DIM0_PAD_L_2,

	CAL_DP_DMA_RD_DIM0_PAD_R_2,

	CAL_DP_DMA_RD_PAD_TB_2,

	CAL_DP_DMA_RD_DIM0_CROP_2,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_2,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_2,

	CAL_DP_DMA_RD_MMU_CFG_2,

	CAL_DP_DMA_RD_PAD_VALUE_2,

	CAL_DP_DMA_RD_CFG_3,

	CAL_DP_DMA_RD_NUM_CMD_IT_3,

	CAL_DP_DMA_RD_START_ADDR_3,

	CAL_DP_DMA_RD_START_ADDR1_3,

	CAL_DP_DMA_RD_END_ADDR0_3,

	CAL_DP_DMA_RD_MAX_ADDR_3,

	CAL_DP_DMA_RD_MAX_ADDR1_3,

	CAL_DP_DMA_RD_STRIDE_DIM0_3,

	CAL_DP_DMA_RD_STRIDE_DIM0_FIRST_3,

	CAL_DP_DMA_RD_STRIDE_DIM1_3,

	CAL_DP_DMA_RD_STRIDE_DIM1_FIRST_3,

	CAL_DP_DMA_RD_STRIDE_DIM2_3,

	CAL_DP_DMA_RD_STRIDE_DIM2_FIRST_3,

	CAL_DP_DMA_RD_ROW_INCR_3,

	CAL_DP_DMA_RD_DIM0_BLK_SIZE_3,

	CAL_DP_DMA_RD_DIM0_INCR_3,

	CAL_DP_DMA_RD_DIM0_NUM_BLK_3,

	CAL_DP_DMA_RD_DIM1_BLK_SIZE_3,

	CAL_DP_DMA_RD_DIM1_STRIPE_SIZE_3,

	CAL_DP_DMA_RD_DIM2_BLK_SIZE_3,

	CAL_DP_DMA_RD_DIM2_STRIPE_SIZE_3,

	CAL_DP_DMA_RD_DIM0_PAD_L_3,

	CAL_DP_DMA_RD_DIM0_PAD_R_3,

	CAL_DP_DMA_RD_PAD_TB_3,

	CAL_DP_DMA_RD_DIM0_CROP_3,

	CAL_DP_DMA_RD_CLIENT_ADDR_CFG_3,

	CAL_DP_DMA_RD_CLIENT_BUFF_CFG_3,

	CAL_DP_DMA_RD_MMU_CFG_3,

	CAL_DP_DMA_RD_PAD_VALUE_3,

	CAL_DP_DMA_LOC_SRC_ADDR_0,

	CAL_DP_DMA_LOC_DEST_ADDR_0,

	CAL_DP_DMA_LOC_DATA_SIZE_0,

	CAL_DP_DMA_WR_ERR_STATUS_0,

	CAL_DP_DMA_WR_MAX_P_CNT_0,

	CAL_DP_DMA_WR_STATUS_0_0,

	CAL_DP_DMA_WR_STATUS_0_1,

	CAL_DP_DMA_WR_STATUS_0_2,

	CAL_DP_DMA_WR_STATUS_0_3,

	CAL_DP_DMA_RD_ERR_STATUS_0,

	CAL_DP_DMA_RD_MAX_P_CNT_0,

	CAL_DP_DMA_RD_STATUS_0_0,

	CAL_DP_DMA_RD_STATUS_0_1,

	CAL_DP_DMA_RD_STATUS_0_2,

	CAL_DP_DMA_RD_STATUS_0_3,

	CAL_DP_DMA_RD_STATUS_0_4,

	CAL_DP_DMA_RD_ERR_STATUS_1,

	CAL_DP_DMA_RD_MAX_P_CNT_1,

	CAL_DP_DMA_RD_STATUS_1_0,

	CAL_DP_DMA_RD_STATUS_1_1,

	CAL_DP_DMA_RD_STATUS_1_2,

	CAL_DP_DMA_RD_STATUS_1_3,

	CAL_DP_DMA_RD_STATUS_1_4,

	CAL_DP_DMA_RD_ERR_STATUS_2,

	CAL_DP_DMA_RD_MAX_P_CNT_2,

	CAL_DP_DMA_RD_STATUS_2_0,

	CAL_DP_DMA_RD_STATUS_2_1,

	CAL_DP_DMA_RD_STATUS_2_2,

	CAL_DP_DMA_RD_STATUS_2_3,

	CAL_DP_DMA_RD_STATUS_2_4,

	CAL_DP_DMA_RD_ERR_STATUS_3,

	CAL_DP_DMA_RD_MAX_P_CNT_3,

	CAL_DP_DMA_RD_STATUS_3_0,

	CAL_DP_DMA_RD_STATUS_3_1,

	CAL_DP_DMA_RD_STATUS_3_2,

	CAL_DP_DMA_RD_STATUS_3_3,

	CAL_DP_DMA_LOC_ERR_STATUS_0,

	CAL_DP_DMA_LOC_STATUS_0_0,

	CAL_DP_DMA_LOC_STATUS_0_1,

	CAL_DP_DMA_LOC_STATUS_0_2,

	CAL_DP_DMA_LOC_STATUS_0_3,

	CAL_DP_CALDMA_ADAPT_STATUS_0_0,

	CAL_DP_CALDMA_ADAPT_STATUS_0_1,

	CAL_DP_SDMA_WR_STATUS_0_0,

	CAL_DP_SDMA_WR_STATUS_0_1,

	CAL_DP_SDMA_WR_STATUS_0_2,

	CAL_DP_SDMA_WR_STATUS_0_3,

	CAL_DP_SDMA_WR_STATUS_0_4,

	CAL_DP_SDMA_WR_STATUS_0_5,

	CAL_DP_SDMA_WR_STATUS_0_6,

	CAL_DP_SDMA_WR_STATUS_0_7,

	CAL_DP_SDMA_WR_STATUS_0_8,

	CAL_DP_SDMA_RD_STATUS_0_0,

	CAL_DP_SDMA_RD_STATUS_0_1,

	CAL_DP_SDMA_RD_STATUS_0_2,

	CAL_DP_SDMA_RD_STATUS_0_3,

	CAL_DP_SDMA_RD_STATUS_0_4,

	CAL_DP_SDMA_RD_STATUS_0_5,

	CAL_DP_SDMA_RD_STATUS_0_6,

	CAL_DP_SDMA_RD_STATUS_0_7,

	CAL_DP_SDMA_RD_STATUS_0_8,

	CAL_DP_SDMA_RD_STATUS_0_9,

	CAL_DP_SDMA_RD_STATUS_0_10,

	CAL_DP_TCM_SET_CMD,

	CAL_DP_TCM_RESET_CMD,

	CAL_DP_DTSWC_INT_CLR,

	CAL_DP_TCM_INT_CLR,

	CAL_DP_DTSWC_INT_SET,

	CAL_DP_TCM_INT_SET,

	CAL_DP_WD_RSS_CMD,

	CAL_DP_RESET_CMD,

	CAL_DP_PERF_CNT_CMD,

	CAL_DP_DBUF_TRANSFER_CMD,

	CAL_DP_CAL_EN_CTRL,

	CAL_DP_EN_INT_CTRL,

	CAL_DP_EN_TCM_INT_CTRL,

	CAL_DP_TCM_VAL_CTRL,

	CAL_DP_WD_COUNT_LO,

	CAL_DP_WD_COUNT_HI,

	CAL_DP_RSS_SEL_CTRL,

	CAL_DP_CAL_CFG_W0,

	CAL_DP_CAL_CFG_W1,

	CAL_DP_CAL_CFG_W2,

	CAL_DP_CAL_CFG_W3,

	CAL_DP_PERF_CNT_START_SEL,

	CAL_DP_PERF_CNT_STOP_SEL,

	CAL_DP_PERF_CNT_EVENT_SEL,

	CAL_DP_DBUF_RD_SEL,

	CAL_DP_LM_CTRL,

	CAL_DP_LM_LOOK_AHEAD,

	CAL_DP_LM_CUB_TIMER,

	CAL_DP_SIGB_STATUS,

	CAL_DP_CAL_EN_WD_RSS_STATUS,

	CAL_DP_EN_TCM_FLAGS_STATUS,

	CAL_DP_VERSION_STATUS,

	CAL_DP_CFG_STATUS,

	CAL_DP_CUB_SAT_DTCT_STATUS,

	CAL_DP_AHB_ERR_ADDR_STATUS,

	CAL_DP_WD_STATUS_LO,

	CAL_DP_WD_STATUS_HI,

	CAL_DP_DTSWC_INT_STATUS,

	CAL_DP_DTSWC_TCM_INT_STATUS,

	CAL_DP_DTSWC_UM_INT_STATUS,

	CAL_DP_DTSWC_TCM_UM_INT_STATUS,

	CAL_DP_RSS_STATUS,

	CAL_DP_RSS_STATUS_1,

	CAL_DP_RSS_STATUS_2,

	CAL_DP_RSS_STATUS_3,

	CAL_DP_RSS_STATUS_4,

	CAL_DP_RSS_STATUS_5,

	CAL_DP_RSS_STATUS_6,

	CAL_DP_RSS_STATUS_7,

	CAL_DP_PERF_CNT0,

	CAL_DP_PERF_CNT1,

	CAL_DP_PERF_CNT2,

	CAL_DP_PERF_CNT3,

	CAL_DP_FINAL_MIN,

	CAL_DP_FINAL_MAX,

	CAL_DP_LM_STATUS

};



/* -------------------------------------------------------------------------

 * Function Definitions - Debug

 * -------------------------------------------------------------------------
@@ -306,39 +37,3 @@ void npu_dump_debug_timeout_stats(struct npu_device *npu_dev) 
	reg_val = REGR(npu_dev, REG_NPU_FW_DEBUG_DATA);

	pr_info("fw jobs aco parser debug = %d\n", reg_val);

}
 


void npu_dump_cal_state(struct npu_device *npu_dev)

{

	uint32_t reg_val;

	uint32_t i;



	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_START_ADDR_0);

	pr_info("DMA RD 0 Addr: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_WR_START_ADDR_0);

	pr_info("DMA WR Addr: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_START_ADDR_1);

	pr_info("DMA RD 1 Addr: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_START_ADDR_2);

	pr_info("DMA RD 2 Addr: 0x%x\n", reg_val);



	/* mask irq status reg */

	reg_val = REGR(npu_dev, CAL_DP_DTSWC_INT_STATUS);

	pr_info("Masked ISR Status: 0x%x\n", reg_val);



	/* unmasked mask irq status reg */

	reg_val = REGR(npu_dev, CAL_DP_DTSWC_UM_INT_STATUS);

	pr_info("UnMasked ISR Status: 0x%x\n", reg_val);



	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_ERR_STATUS_0);

	pr_info("rd err 0 Status: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_ERR_STATUS_1);

	pr_info("rd err 1 Status: 0x%x\n", reg_val);

	reg_val = REGR(npu_dev, CAL_DP_DMA_RD_ERR_STATUS_2);

	pr_info("rd err 2 Status: 0x%x\n", reg_val);



	for (i = 0; i < sizeof(debug_cal_reg_list) / sizeof(uint32_t); i++) {

		reg_val = REGR(npu_dev, debug_cal_reg_list[i]);

		pr_info("Reg = 0x%x Val = 0x%x\n", debug_cal_reg_list[i],

			reg_val);

	}

}

drivers/media/platform/msm/npu/npu_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -169,7 +169,7 @@ static ssize_t npu_debug_reg_read(struct file *file, 
		if (!debugfs->buf)

			return -ENOMEM;



		ptr = npu_dev->npu_io.base + debugfs->reg_off;

		ptr = npu_dev->core_io.base + debugfs->reg_off;

		tot = 0;

		off = (int)debugfs->reg_off;
@@ -183,7 +183,7 @@ static ssize_t npu_debug_reg_read(struct file *file, 
			len = scnprintf(debugfs->buf + tot,

				debugfs->buf_len - tot, "0x%08x: %s\n",

				((int) (unsigned long) ptr) -

				((int) (unsigned long) npu_dev->npu_io.base),

				((int) (unsigned long) npu_dev->core_io.base),

				dump_buf);



			ptr += ROW_BYTES;

drivers/media/platform/msm/npu/npu_dev.c

+54 −11
Original line number Diff line number Diff line
@@ -709,8 +709,11 @@ static void npu_save_bw_registers(struct npu_device *npu_dev) 
{

	int i;



	if (!npu_dev->bwmon_io.base)

		return;



	for (i = 0; i < ARRAY_SIZE(npu_saved_bw_registers); i++) {

		npu_saved_bw_registers[i].val = REGR(npu_dev,

		npu_saved_bw_registers[i].val = npu_bwmon_reg_read(npu_dev,

			npu_saved_bw_registers[i].off);

		npu_saved_bw_registers[i].valid = true;

	}
@@ -720,9 +723,13 @@ static void npu_restore_bw_registers(struct npu_device *npu_dev) 
{

	int i;



	if (!npu_dev->bwmon_io.base)

		return;



	for (i = 0; i < ARRAY_SIZE(npu_saved_bw_registers); i++) {

		if (npu_saved_bw_registers[i].valid) {

			REGW(npu_dev, npu_saved_bw_registers[i].off,

			npu_bwmon_reg_write(npu_dev,

				npu_saved_bw_registers[i].off,

				npu_saved_bw_registers[i].val);

			npu_saved_bw_registers[i].valid = false;

		}
@@ -1904,22 +1911,58 @@ static int npu_probe(struct platform_device *pdev) 


	platform_set_drvdata(pdev, npu_dev);

	res = platform_get_resource_byname(pdev,

		IORESOURCE_MEM, "npu_base");

		IORESOURCE_MEM, "core");

	if (!res) {

		pr_err("unable to get core resource\n");

		rc = -ENODEV;

		goto error_get_dev_num;

	}

	npu_dev->core_io.size = resource_size(res);

	npu_dev->core_io.base = devm_ioremap(&pdev->dev, res->start,

					npu_dev->core_io.size);

	if (unlikely(!npu_dev->core_io.base)) {

		pr_err("unable to map core\n");

		rc = -ENOMEM;

		goto error_get_dev_num;

	}

	pr_debug("core phy address=0x%x virt=%pK\n",

		res->start, npu_dev->core_io.base);



	res = platform_get_resource_byname(pdev,

		IORESOURCE_MEM, "tcm");

	if (!res) {

		pr_err("unable to get tcm resource\n");

		rc = -ENODEV;

		goto error_get_dev_num;

	}

	npu_dev->tcm_io.size = resource_size(res);

	npu_dev->tcm_io.base = devm_ioremap(&pdev->dev, res->start,

					npu_dev->tcm_io.size);

	if (unlikely(!npu_dev->tcm_io.base)) {

		pr_err("unable to map tcm\n");

		rc = -ENOMEM;

		goto error_get_dev_num;

	}

	pr_debug("core phy address=0x%x virt=%pK\n",

		res->start, npu_dev->tcm_io.base);



	res = platform_get_resource_byname(pdev,

		IORESOURCE_MEM, "bwmon");

	if (!res) {

		pr_err("unable to get npu_base resource\n");

		pr_err("unable to get bwmon resource\n");

		rc = -ENODEV;

		goto error_get_dev_num;

	}

	npu_dev->npu_io.size = resource_size(res);

	npu_dev->npu_io.base = devm_ioremap(&pdev->dev, res->start,

					npu_dev->npu_io.size);

	if (unlikely(!npu_dev->npu_io.base)) {

		pr_err("unable to map npu_base\n");

	npu_dev->bwmon_io.size = resource_size(res);

	npu_dev->bwmon_io.base = devm_ioremap(&pdev->dev, res->start,

					npu_dev->bwmon_io.size);

	if (unlikely(!npu_dev->bwmon_io.base)) {

		pr_err("unable to map bwmon\n");

		rc = -ENOMEM;

		goto error_get_dev_num;

	}

	pr_debug("npu_base phy address=0x%x virt=%pK\n",

		res->start, npu_dev->npu_io.base);

	pr_debug("bwmon phy address=0x%x virt=%pK\n",

		res->start, npu_dev->bwmon_io.base);



	res = platform_get_resource_byname(pdev,

		IORESOURCE_MEM, "qfprom_physical");

drivers/media/platform/msm/npu/npu_hw.h

+28 −291

File changed.

Preview size limit exceeded, changes collapsed.