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Commit 8010bb0b authored by Jilai Wang's avatar Jilai Wang
Browse files

ARM: msm: dts: Update npu clocks and io spaces 



This change is to separate "npu_base" io space into "core/tcm/bwmon"
io spaces in order to support npu on different chips. It also updates
the clocks based on power on sequence.

Change-Id: I744610f821c17d73de654b08a24962bf552cf3af
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 94da5973

arch/arm64/boot/dts/qcom/sdmmagpie-npu.dtsi

+67 −65
Original line number Diff line number Diff line
@@ -13,9 +13,11 @@ 
&soc {

	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		reg = <0x9800000 0x800000>,

		reg = <0x9900000 0x40000>,

			<0x9900000 0x10000>,

			<0x9960200 0x600>,

			<0x780000 0x7000>;

		reg-names = "npu_base", "qfprom_physical";

		reg-names = "tcm", "core", "bwmon", "qfprom_physical";

		interrupts = <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 587 IRQ_TYPE_EDGE_RISING>;
@@ -24,42 +26,42 @@ 
		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;



		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>,

		clocks = <&clock_aop QDSS_CLK>,

			<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

			<&clock_npucc NPU_CC_BTO_CORE_CLK>,

			<&clock_npucc NPU_CC_BWMON_CLK>,

			<&clock_npucc NPU_CC_CAL_DP_CLK>,

			<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,

			<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

			<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

			<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

			<&clock_npucc NPU_CC_NPU_CPC_CLK>,

			<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

			<&clock_npucc NPU_CC_PERF_CNT_CLK>,

			<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

			<&clock_npucc NPU_CC_SLEEP_CLK>,

			<&clock_aop QDSS_CLK>;

		clock-names = "cal_dp_clk",

			"xo_clk",

			<&clock_npucc NPU_CC_BWMON_CLK>,

			<&clock_npucc NPU_CC_PERF_CNT_CLK>,

			<&clock_npucc NPU_CC_BTO_CORE_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>;

		clock-names = "qdss_clk",

			"armwic_core_clk",

			"bto_core_clk",

			"bwmon_clk",

			"cal_dp_clk",

			"cal_dp_cdc_clk",

			"comp_noc_axi_clk",

			"conf_noc_ahb_clk",

			"npu_core_apb_clk",

			"npu_core_atb_clk",

			"comp_noc_axi_clk",

			"npu_core_clk",

			"npu_core_cti_clk",

			"npu_core_apb_clk",

			"npu_core_atb_clk",

			"npu_cpc_clk",

			"npu_cpc_timer_clk",

			"perf_cnt_clk",

			"qtimer_core_clk",

			"sleep_clk",

			"qdss_clk";

			"bwmon_clk",

			"perf_cnt_clk",

			"bto_core_clk",

			"xo_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";
@@ -77,112 +79,112 @@ 
			qcom,npu-pwrlevel@0 {

				reg = <0>;

				vreg = <1>;

				clk-freq = <300000000

					19200000

				clk-freq = <0

					100000000

					19200000

					19200000

					300000000

					150000000

					300000000

					30000000

					19200000

					60000000

					150000000

					100000000

					37500000

					19200000

					60000000

					100000000

					19200000

					300000000

					19200000

					0

					0>;

					19200000

					300000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				vreg = <2>;

				clk-freq = <400000000

					19200000

				clk-freq = <0

					150000000

					19200000

					19200000

					400000000

					200000000

					400000000

					37500000

					19200000

					120000000

					200000000

					150000000

					75000000

					19200000

					120000000

					150000000

					19200000

					400000000

					19200000

					0

					0>;

					19200000

					400000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				vreg = <3>;

				clk-freq = <466500000

					19200000

				clk-freq = <0

					200000000

					19200000

					19200000

					466500000

					300000000

					466500000

					37500000

					19200000

					120000000

					300000000

					200000000

					75000000

					19200000

					120000000

					200000000

					19200000

					466500000

					19200000

					0

					0>;

					19200000

					466500000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				vreg = <4>;

				clk-freq = <600000000

					19200000

				clk-freq = <0

					300000000

					19200000

					19200000

					600000000

					403000000

					600000000

					75000000

					19200000

					240000000

					403000000

					300000000

					150000000

					19200000

					240000000

					300000000

					19200000

					600000000

					19200000

					0

					0>;

					19200000

					600000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				vreg = <6>;

				clk-freq = <700000000

					19200000

				clk-freq = <0

					400000000

					19200000

					19200000

					700000000

					533000000

					700000000

					75000000

					19200000

					300000000

					533000000

					400000000

					150000000

					19200000

					300000000

					400000000

					19200000

					700000000

					19200000

					0

					0>;

					19200000

					700000000

					19200000

					19200000>;

			};

		};

	};

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+126 −124
Original line number Diff line number Diff line
@@ -14,8 +14,10 @@ 
	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		status = "ok";

		reg = <0x9800000 0x800000>;

		reg-names = "npu_base";

		reg = <0x9800000 0x40000>,

			<0x9900000 0x10000>,

			<0x9960200 0x600>;

		reg-names = "tcm", "core", "bwmon";

		interrupts = <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
@@ -23,46 +25,46 @@ 
		iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;

		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;

		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

				<&clock_npucc NPU_CC_XO_CLK>,

		clocks = <&clock_aop QDSS_CLK>,

				<&clock_gcc GCC_NPU_AT_CLK>,

				<&clock_gcc GCC_NPU_TRIG_CLK>,

				<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,

				<&clock_npucc NPU_CC_BWMON_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,

				<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

				<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

				<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

				<&clock_npucc NPU_CC_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

				<&clock_npucc NPU_CC_SLEEP_CLK>,

				<&clock_gcc GCC_NPU_AT_CLK>,

				<&clock_gcc GCC_NPU_TRIG_CLK>,

				<&clock_aop QDSS_CLK>;

		clock-names = "cal_dp_clk",

				"xo_clk",

				<&clock_npucc NPU_CC_BWMON_CLK>,

				<&clock_npucc NPU_CC_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,

				<&clock_npucc NPU_CC_XO_CLK>;

		clock-names = "qdss_clk",

				"at_clk",

				"trig_clk",

				"armwic_core_clk",

				"bto_core_clk",

				"bwmon_clk",

				"cal_dp_clk",

				"cal_dp_cdc_clk",

				"comp_noc_axi_clk",

				"conf_noc_ahb_clk",

				"npu_core_apb_clk",

				"npu_core_atb_clk",

				"comp_noc_axi_clk",

				"npu_core_clk",

				"npu_core_cti_clk",

				"npu_core_apb_clk",

				"npu_core_atb_clk",

				"npu_cpc_clk",

				"npu_cpc_timer_clk",

				"perf_cnt_clk",

				"qtimer_core_clk",

				"sleep_clk",

				"at_clk",

				"trig_clk",

				"qdss_clk";

				"bwmon_clk",

				"perf_cnt_clk",

				"bto_core_clk",

				"xo_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";
@@ -80,122 +82,122 @@ 
			qcom,npu-pwrlevel@0 {

				reg = <0>;

				vreg = <1>;

				clk-freq = <300000000

						19200000

				clk-freq = <0

					0

					0

					100000000

						19200000

						19200000

					300000000

						150000000

						19200000

					300000000

					19200000

						60000000

					150000000

					100000000

					37500000

					19200000

					60000000

					100000000

					19200000

						300000000

					19200000

					0

						0

						0

						0>;

					19200000

					300000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				vreg = <2>;

				clk-freq = <350000000

						19200000

				clk-freq = <0

					0

					0

					150000000

						19200000

						19200000

					350000000

						200000000

					350000000

					37500000

						19200000

						120000000

					200000000

					150000000

					75000000

					19200000

					120000000

					150000000

					19200000

						350000000

					19200000

					0

						0

						0

						0>;

					19200000

					350000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				vreg = <3>;

				clk-freq = <400000000

						19200000

				clk-freq = <0

					0

					0

					200000000

						19200000

						19200000

					400000000

						300000000

					400000000

					37500000

						19200000

						120000000

					300000000

					200000000

					75000000

					19200000

					120000000

					200000000

					19200000

						400000000

					19200000

					0

						0

						0

						0>;

					19200000

					400000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				vreg = <4>;

				clk-freq = <600000000

						19200000

				clk-freq = <0

					0

					0

					300000000

						19200000

						19200000

					600000000

						403000000

					600000000

					75000000

						19200000

						240000000

					403000000

					300000000

					150000000

					19200000

					240000000

					300000000

					19200000

						600000000

					19200000

					0

						0

						0

						0>;

					19200000

					600000000

					19200000

					19200000>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				vreg = <6>;

				clk-freq = <715000000

						19200000

				clk-freq = <0

					0

					0

					350000000

						19200000

						19200000

					715000000

						533000000

					715000000

					75000000

						19200000

						240000000

					533000000

					350000000

					150000000

					19200000

					240000000

					350000000

					19200000

						715000000

					19200000

					0

						0

						0

						0>;

					19200000

					715000000

					19200000

					19200000>;

			};

		};

	};

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+120 −120
Original line number Diff line number Diff line
@@ -709,146 +709,146 @@ 
		qcom,npu-pwrlevel@0 {

			reg = <0>;

			vreg = <1>;

			clk-freq = <300000000

					19200000

			clk-freq = <0

				0

				0

				100000000

					19200000

					19200000

				300000000

					150000000

					19200000

				300000000

				19200000

					60000000

				150000000

				100000000

				37500000

				19200000

				60000000

				100000000

				19200000

					300000000

				19200000

				0

					0

					0

					0>;

				19200000

				300000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@1 {

			reg = <1>;

			vreg = <2>;

			clk-freq = <400000000

					19200000

			clk-freq = <0

				0

				0

				150000000

					19200000

					19200000

				400000000

					200000000

				400000000

				37500000

					19200000

					120000000

				200000000

				150000000

				75000000

				19200000

				120000000

				150000000

				19200000

					400000000

				19200000

				0

					0

					0

					0>;

				19200000

				400000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@2 {

			reg = <2>;

			vreg = <3>;

			clk-freq = <487000000

					19200000

			clk-freq = <0

				0

				0

				200000000

					19200000

					19200000

				487000000

					300000000

				487000000

				37500000

					19200000

					240000000

				300000000

				200000000

				150000000

				19200000

				240000000

				200000000

				19200000

					487000000

				19200000

				0

					0

					0

					0>;

				19200000

				487000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@3 {

			reg = <3>;

			vreg = <4>;

			clk-freq = <652000000

					19200000

			clk-freq = <0

				0

				0

				300000000

					19200000

					19200000

				652000000

					403000000

				652000000

				75000000

					19200000

					240000000

				403000000

				300000000

				150000000

				19200000

				240000000

				300000000

				19200000

					652000000

				19200000

				0

					0

					0

					0>;

				19200000

				652000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@4 {

			reg = <4>;

			vreg = <6>;

			clk-freq = <811000000

					19200000

			clk-freq = <0

				0

				0

				400000000

					19200000

					19200000

				811000000

					533000000

				811000000

				75000000

					19200000

					300000000

				533000000

				400000000

				150000000

				19200000

				300000000

				400000000

				19200000

					811000000

				19200000

				0

					0

					0

					0>;

				19200000

				811000000

				19200000

				19200000>;

		};

		qcom,npu-pwrlevel@5 {

			reg = <5>;

			vreg = <7>;

			clk-freq = <908000000

					19200000

			clk-freq = <0

				0

				0

				400000000

					19200000

					19200000

				908000000

					533000000

				908000000

				75000000

					19200000

					300000000

				533000000

				400000000

				150000000

				19200000

				300000000

				400000000

				19200000

					908000000

				19200000

				0

					0

					0

					0>;

				19200000

				908000000

				19200000

				19200000>;

		};

	};

};