Loading sound/soc/codecs/wm_adsp.c +22 −0 Original line number Diff line number Diff line Loading @@ -544,6 +544,28 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_POST_PMU: /* * For simplicity set the DSP clock rate to be the * SYSCLK rate rather than making it configurable. */ ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val); if (ret != 0) { adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); return ret; } val = (val & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT; ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, ADSP2_CLK_SEL_MASK, val); if (ret != 0) { adsp_err(dsp, "Failed to set clock rate: %d\n", ret); return ret; } if (dsp->dvfs) { ret = regmap_read(dsp->regmap, dsp->base + ADSP2_CLOCKING, &val); Loading Loading
sound/soc/codecs/wm_adsp.c +22 −0 Original line number Diff line number Diff line Loading @@ -544,6 +544,28 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_POST_PMU: /* * For simplicity set the DSP clock rate to be the * SYSCLK rate rather than making it configurable. */ ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val); if (ret != 0) { adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); return ret; } val = (val & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT; ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, ADSP2_CLK_SEL_MASK, val); if (ret != 0) { adsp_err(dsp, "Failed to set clock rate: %d\n", ret); return ret; } if (dsp->dvfs) { ret = regmap_read(dsp->regmap, dsp->base + ADSP2_CLOCKING, &val); Loading