Merge "ARM: dts: msm: Add SSC QUPV3 I2C device nodes for SM6150" (d498efb8) · Commits · e / devices / android_kernel_xiaomi_sm6125

arch/arm64/boot/dts/qcom/sm6150-qupv3.dtsi

+156 −0

Original line number	Diff line number	Diff line
		@@ -325,4 +325,160 @@
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_1>;
		};

		/* QUPv3 SSC Instances */
		qupv3_2: qcom,qupv3_2_geni_se@626c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x626c0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_LPASS_ANOC>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;

		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {
		compatible = "qcom,qupv3-geni-se-cb";
		iommus = <&apps_smmu 0x1783 0x0>;
		};
		};

		/* I2C */
		qupv3_se8_i2c: i2c@62680000 {
		compatible = "qcom,i2c-geni";
		reg = <0x62680000 0x4000>;
		interrupts = <GIC_SPI 442 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE0_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_i2c_active>;
		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};

		qupv3_se9_i2c: i2c@62684000 {
		compatible = "qcom,i2c-geni";
		reg = <0x62684000 0x4000>;
		interrupts = <GIC_SPI 443 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_i2c_active>;
		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};

		qupv3_se10_i2c: i2c@62688000 {
		compatible = "qcom,i2c-geni";
		reg = <0x62688000 0x4000>;
		interrupts = <GIC_SPI 444 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_i2c_active>;
		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};

		qupv3_se11_i2c: i2c@6268c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x6268c000 0x4000>;
		interrupts = <GIC_SPI 445 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE3_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se11_i2c_active>;
		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};

		qupv3_se12_i2c: i2c@62690000 {
		compatible = "qcom,i2c-geni";
		reg = <0x62690000 0x4000>;
		interrupts = <GIC_SPI 446 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE4_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se12_i2c_active>;
		pinctrl-1 = <&qupv3_se12_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};

		qupv3_se13_i2c: i2c@62694000 {
		compatible = "qcom,i2c-geni";
		reg = <0x62694000 0x4000>;
		interrupts = <GIC_SPI 447 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE5_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se13_i2c_active>;
		pinctrl-1 = <&qupv3_se13_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};

		/* SPI */
		qupv3_se9_spi: spi@62684000 {
		compatible = "qcom,spi-geni";
		reg = <0x62684000 0x4000>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 443 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_spi_active>;
		pinctrl-1 = <&qupv3_se9_spi_sleep>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};

		qupv3_se10_spi: spi@62688000 {
		compatible = "qcom,spi-geni";
		reg = <0x62688000 0x4000>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 444 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,
		<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
		<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_spi_active>;
		pinctrl-1 = <&qupv3_se10_spi_sleep>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
		};
		};

arch/arm64/boot/dts/qcom/sm6150-slpi-pinctrl.dtsi

+232 −0

Original line number	Diff line number	Diff line
		@@ -16,5 +16,237 @@
		reg = <0x62B40000 0x20000>;
		qcom,num-pins = <32>;
		status = "disabled";

		qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
		qupv3_se8_i2c_active: qupv3_se8_i2c_active {
		mux {
		pins = "gpio0", "gpio1";
		function = "func1";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
		mux {
		pins = "gpio0", "gpio1";
		function = "gpio";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
		qupv3_se9_i2c_active: qupv3_se9_i2c_active {
		mux {
		pins = "gpio2", "gpio3";
		function = "func1";
		};

		config {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
		mux {
		pins = "gpio2", "gpio3";
		function = "gpio";
		};

		config {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
		qupv3_se10_i2c_active: qupv3_se10_i2c_active {
		mux {
		pins = "gpio8", "gpio9";
		function = "func1";
		};

		config {
		pins = "gpio8", "gpio9";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
		mux {
		pins = "gpio8", "gpio9";
		function = "gpio";
		};

		config {
		pins = "gpio8", "gpio9";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
		qupv3_se11_i2c_active: qupv3_se11_i2c_active {
		mux {
		pins = "gpio16", "gpio17";
		function = "func3";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
		mux {
		pins = "gpio16", "gpio17";
		function = "gpio";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
		qupv3_se12_i2c_active: qupv3_se12_i2c_active {
		mux {
		pins = "gpio16", "gpio17";
		function = "func2";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
		mux {
		pins = "gpio16", "gpio17";
		function = "gpio";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
		qupv3_se13_i2c_active: qupv3_se13_i2c_active {
		mux {
		pins = "gpio14", "gpio15";
		function = "func2";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
		mux {
		pins = "gpio14", "gpio15";
		function = "gpio";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se9_spi_pins: qupv3_se9_spi_pins {
		qupv3_se9_spi_active: qupv3_se9_spi_active {
		mux {
		pins = "gpio2", "gpio3", "gpio4",
		"gpio5";
		function = "func1";
		};

		config {
		pins = "gpio2", "gpio3", "gpio4",
		"gpio5";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
		mux {
		pins = "gpio2", "gpio3", "gpio4",
		"gpio5";
		function = "gpio";
		};

		config {
		pins = "gpio2", "gpio3", "gpio4",
		"gpio5";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		qupv3_se10_spi_pins: qupv3_se10_spi_pins {
		qupv3_se10_spi_active: qupv3_se10_spi_active {
		mux {
		pins = "gpio8", "gpio9", "gpio10",
		"gpio11";
		function = "func1";
		};

		config {
		pins = "gpio8", "gpio9", "gpio10",
		"gpio11";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
		mux {
		pins = "gpio8", "gpio9", "gpio10",
		"gpio11";
		function = "gpio";
		};

		config {
		pins = "gpio8", "gpio9", "gpio10",
		"gpio11";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};
		};
		};