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Commit 9ff2a7bf authored by Ajay Agarwal's avatar Ajay Agarwal
Browse files

ARM: dts: msm: Add SSC QUPV3 I2C device nodes for SM6150 



Add device tree nodes for SSC QUPv3 I2C serial engines required
for I2C usecases on SSC QUP to be accessed by HLOS.

Change-Id: Idb6af61db77d04b8701174d56a4de9adfbe5365b
Signed-off-by: default avatarAjay Agarwal <ajaya@codeaurora.org>
parent 467289ca

arch/arm64/boot/dts/qcom/sm6150-qupv3.dtsi

+103 −0
Original line number Diff line number Diff line
@@ -340,6 +340,109 @@ 
		};

	};



	/* I2C */

	qupv3_se8_i2c: i2c@62680000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62680000 0x4000>;

		interrupts = <GIC_SPI 442 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE0_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se8_i2c_active>;

		pinctrl-1 = <&qupv3_se8_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se9_i2c: i2c@62684000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62684000 0x4000>;

		interrupts = <GIC_SPI 443 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se9_i2c_active>;

		pinctrl-1 = <&qupv3_se9_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se10_i2c: i2c@62688000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62688000 0x4000>;

		interrupts = <GIC_SPI 444 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se10_i2c_active>;

		pinctrl-1 = <&qupv3_se10_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se11_i2c: i2c@6268c000 {

		compatible = "qcom,i2c-geni";

		reg = <0x6268c000 0x4000>;

		interrupts = <GIC_SPI 445 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE3_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se11_i2c_active>;

		pinctrl-1 = <&qupv3_se11_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se12_i2c: i2c@62690000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62690000 0x4000>;

		interrupts = <GIC_SPI 446 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE4_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se12_i2c_active>;

		pinctrl-1 = <&qupv3_se12_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se13_i2c: i2c@62694000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62694000 0x4000>;

		interrupts = <GIC_SPI 447 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE5_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se13_i2c_active>;

		pinctrl-1 = <&qupv3_se13_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	/* SPI */

	qupv3_se9_spi: spi@62684000 {

		compatible = "qcom,spi-geni";

arch/arm64/boot/dts/qcom/sm6150-slpi-pinctrl.dtsi

+168 −0
Original line number Diff line number Diff line
@@ -17,6 +17,174 @@ 
		qcom,num-pins = <32>;

		status = "disabled";



		qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {

			qupv3_se8_i2c_active: qupv3_se8_i2c_active {

				mux {

					pins = "gpio0", "gpio1";

					function = "func1";

				};



				config {

					pins = "gpio0", "gpio1";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {

				mux {

					pins = "gpio0", "gpio1";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {

			qupv3_se9_i2c_active: qupv3_se9_i2c_active {

				mux {

					pins = "gpio2", "gpio3";

					function = "func1";

				};



				config {

					pins = "gpio2", "gpio3";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {

				mux {

					pins = "gpio2", "gpio3";

					function = "gpio";

				};



				config {

					pins = "gpio2", "gpio3";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {

			qupv3_se10_i2c_active: qupv3_se10_i2c_active {

				mux {

					pins = "gpio8", "gpio9";

					function = "func1";

				};



				config {

					pins = "gpio8", "gpio9";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {

				mux {

					pins = "gpio8", "gpio9";

					function = "gpio";

				};



				config {

					pins = "gpio8", "gpio9";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {

			qupv3_se11_i2c_active: qupv3_se11_i2c_active {

				mux {

					pins = "gpio16", "gpio17";

					function = "func3";

				};



				config {

					pins = "gpio16", "gpio17";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {

				mux {

					pins = "gpio16", "gpio17";

					function = "gpio";

				};



				config {

					pins = "gpio16", "gpio17";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {

			qupv3_se12_i2c_active: qupv3_se12_i2c_active {

				mux {

					pins = "gpio16", "gpio17";

					function = "func2";

				};



				config {

					pins = "gpio16", "gpio17";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {

				mux {

					pins = "gpio16", "gpio17";

					function = "gpio";

				};



				config {

					pins = "gpio16", "gpio17";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {

			qupv3_se13_i2c_active: qupv3_se13_i2c_active {

				mux {

					pins = "gpio14", "gpio15";

					function = "func2";

				};



				config {

					pins = "gpio14", "gpio15";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {

				mux {

					pins = "gpio14", "gpio15";

					function = "gpio";

				};



				config {

					pins = "gpio14", "gpio15";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se9_spi_pins: qupv3_se9_spi_pins {

			qupv3_se9_spi_active: qupv3_se9_spi_active {

				mux {