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Commit 467289ca authored by Ajay Agarwal's avatar Ajay Agarwal
Browse files

ARM: dts: msm: Add SSC QUPV3 SPI device nodes for SM6150 



Add device tree nodes for SSC QUPv3 and child SPI serial engines
required for access of SSC QUP by HLOS.

Change-Id: Ie21ecf1c4b7f64ed590b4ea5086e5d7542130db6
Signed-off-by: default avatarAjay Agarwal <ajaya@codeaurora.org>
parent e0615925

arch/arm64/boot/dts/qcom/sm6150-qupv3.dtsi

+53 −0
Original line number Diff line number Diff line
@@ -325,4 +325,57 @@ 
		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_1>;

	};



	/* QUPv3 SSC Instances */

	qupv3_2: qcom,qupv3_2_geni_se@626c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x626c0000 0x6000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_LPASS_ANOC>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;



		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x1783 0x0>;

		};

	};



	/* SPI */

	qupv3_se9_spi: spi@62684000 {

		compatible = "qcom,spi-geni";

		reg = <0x62684000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 443 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se9_spi_active>;

		pinctrl-1 = <&qupv3_se9_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se10_spi: spi@62688000 {

		compatible = "qcom,spi-geni";

		reg = <0x62688000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 444 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se10_spi_active>;

		pinctrl-1 = <&qupv3_se10_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};

};

arch/arm64/boot/dts/qcom/sm6150-slpi-pinctrl.dtsi

+64 −0
Original line number Diff line number Diff line
@@ -16,5 +16,69 @@ 
		reg = <0x62B40000 0x20000>;

		qcom,num-pins = <32>;

		status = "disabled";



		qupv3_se9_spi_pins: qupv3_se9_spi_pins {

			qupv3_se9_spi_active: qupv3_se9_spi_active {

				mux {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					function = "func1";

				};



				config {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {

				mux {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					function = "gpio";

				};



				config {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se10_spi_pins: qupv3_se10_spi_pins {

			qupv3_se10_spi_active: qupv3_se10_spi_active {

				mux {

					pins = "gpio8", "gpio9", "gpio10",

								"gpio11";

					function = "func1";

				};



				config {

					pins = "gpio8", "gpio9", "gpio10",

								"gpio11";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {

				mux {

					pins = "gpio8", "gpio9", "gpio10",

								"gpio11";

					function = "gpio";

				};



				config {

					pins = "gpio8", "gpio9", "gpio10",

								"gpio11";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};

	};

};