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Commit b23b8aad authored by Saurabh Sahu's avatar Saurabh Sahu
Browse files

ARM: dts: msm: Add CPU clock support for sdm429w 



Add clock_cpu node for sdm429w for client to able
to request clocks for CPU scaling.

Change-Id: Ief6e4ddc7553cd04656347713f62a1299b13935b
Signed-off-by: default avatarSaurabh Sahu <sausah@codeaurora.org>
parent 5dda24b0

arch/arm64/boot/dts/qcom/sdm429.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/mdss-12nm-pll-clk.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

#include <dt-bindings/clock/qcom,cpu-sdm.h>



/ {

	model = "Qualcomm Technologies, Inc. SDM429";
@@ -341,6 +342,75 @@ 
		#clock-cells = <1>;

	};



	cpu: qcom,clock-cpu@b011050 {

		compatible = "qcom,cpu-clock-sdm";

		reg =   <0xb011050 0x8>,

			<0xb1d1050 0x8>,

			<0xB016000 0x34>,

			<0x00a412c 0x8>;

		reg-names = "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "apcs_pll", "efuse";

		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,

			<&gcc GPLL0_AO_OUT_MAIN>;

		clock-names = "xo_ao", "gpll0_ao" ;

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_hf_pll-supply = <&L12A_AO>;

		vdd_dig_ao-supply = <&VDD_CX_LEVEL_AO>;

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed1-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1804800000 5>;



		qcom,speed1-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed4-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>,

			< 2016000000 6>;



		qcom,speed4-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed5-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>;



		qcom,speed5-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		#clock-cells = <1>;

	};



	cpu-pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <1 7 0xff00>;