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Commit 5dda24b0 authored by Saurabh Sahu's avatar Saurabh Sahu
Browse files

clk: qcom: cpu-sdm: Add cpu clock driver for SDM 



Add support for CPU clock driver for scaling of cpu
clocks on sdm targets.

Change-Id: I9ab83b02052ab9b3e4342bc72380df799fb86976
Signed-off-by: default avatarSaurabh Sahu <sausah@codeaurora.org>
parent 15c00787

Documentation/devicetree/bindings/clock/qcom,sdm-cpucc.txt

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Qualcomm Technologies, Inc. SDM CPU clock driver

---------------------------------------------------



It is the clock controller driver which provides higher frequency

clocks and allows CPU frequency scaling on sdm based platforms.



Required properties:

- compatible:	Shall contain following:

		"qcom,cpu-clock-sdm"

- clocks:	Phandle to the clock device.

- clock-names:	Names of the used clocks. Shall contain following:

		"xo_ao", "gpll0_ao"

- reg:	Shall contain base register offset and size.

- reg-names:	Names of the bases for the above registers. Shall contain following:

		"apcs-c1-rcg-base", "apcs-cci-rcg-base", "apcs_pll", "efuse"

- vdd_dig_ao-supply:	The regulator(active only) powering the digital logic of APSS PLL.

- vdd_hf_pll-supply:	The regulator(active only) powering the Analog logic of APSS PLL.

- cpu-vdd-supply:	The regulator powering the APSS C1 RCG and APSS CCI RCG.

- qcom,speedX-bin-vY-Z:	A table of CPU frequency (Hz) to regulator voltage (uV) mapping.

			Format: <freq uV>

			This represents the max frequency possible for each possible

			power configuration for a CPU that's binned as speed bin X,

			speed bin revision Y. Version can be between [0-3]. Z

			is the mux id c1 or cci.

- #clock-cells:	Shall contain 1.



Example:

	clock_cpu: qcom,clock-cpu@0b011050 {

		compatible = "qcom,cpu-clock-sdm";

		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,

			<&gcc GPLL0_AO_OUT_MAIN>;

		clock-names = "xo_ao", "gpll0_ao" ;

		reg =   <0xb011050 0x8>,

			<0xb1d1050 0x8>,

			<0xb016000 0x34>,

			<0x00a412c 0x8>;

		reg-names = "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "apcs_pll", "efuse";

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_dig_ao-supply = <&L12A_AO;

		vdd_hf_pll-supply = <&VDD_CX_LEVEL_AO>;

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed1-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1804800000 5>;



		qcom,speed1-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed4-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>,

			< 2016000000 6>;



		qcom,speed4-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed5-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>;



		qcom,speed5-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		#clock-cells = <1>;

	};

drivers/clk/qcom/Kconfig

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@@ -688,3 +688,11 @@ config SDM_DEBUGCC_429W 
	  Support for the debug clock controller on Qualcomm Technologies, Inc

	  SDM429W devices.

	  Say Y if you want to support the clock measurement functionality.



config CLOCK_CPU_SDM

	bool "CPU SDM Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	 Support for the cpu clock controller on SDM based devices(e.g. SDM429).

	 Say Y if you want to support CPU clock scaling using

	 CPUfreq drivers for dynamic power management.

drivers/clk/qcom/Makefile

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@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o 
obj-$(CONFIG_CLOCK_CPU_OSM) += clk-cpu-osm.o

obj-$(CONFIG_CLOCK_CPU_OSM_660) += clk-cpu-osm-660.o

obj-$(CONFIG_CLOCK_CPU_QCS405) += clk-cpu-qcs405.o

obj-$(CONFIG_CLOCK_CPU_SDM) += clk-cpu-sdm.o

obj-$(CONFIG_CLOCK_CPU_SDXPRAIRIE) += clk-cpu-sdxprairie.o

obj-$(CONFIG_DEBUGCC_SDXPRAIRIE) += debugcc-sdxprairie.o

obj-$(CONFIG_GCC_SDXPRAIRIE) += gcc-sdxprairie.o

drivers/clk/qcom/clk-cpu-sdm.c

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File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/qcom/vdd-level-cpu.h

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/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_CPU_H

#define __DRIVERS_CLK_QCOM_VDD_LEVEL_CPU_H



#include <linux/regulator/rpm-smd-regulator.h>

#include <linux/regulator/consumer.h>



enum vdd_hf_pll_levels {

	VDD_HF_PLL_OFF,

	VDD_HF_PLL_SVS,

	VDD_HF_PLL_NOM,

	VDD_HF_PLL_TUR,

	VDD_HF_PLL_NUM,

};



static int vdd_hf_levels[] = {

	0,	 RPM_REGULATOR_LEVEL_NONE,	/* VDD_HF_PLL_OFF */

	1800000, RPM_REGULATOR_LEVEL_SVS,	/* VDD_HF_PLL_SVS */

	1800000, RPM_REGULATOR_LEVEL_NOM,	/* VDD_HF_PLL_NOM */

	1800000, RPM_REGULATOR_LEVEL_TURBO,	/* VDD_HF_PLL_TUR */

};



#endif