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Commit 925a36b0 authored by Prakash Gupta's avatar Prakash Gupta Committed by Gerrit - the friendly Code Review server
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iommu: arm-smmu: reset CBn FSR while device reset 



commit 8cd0b952aaa9 ("iommu/arm-smmu: add DT option to skip certain
initialization"), skipped FSR clearing at the time of device reset. This
works if HW resets FSR. Otherwise FSR may have unknown value out of device
reset, this can cause spurious fault when context bank is enabled. Clear
any pending faults in CBn FSR while device reset.

Change-Id: I8402f77958a29b40e8119528eed432ada1414d6b
Signed-off-by: default avatarPrakash Gupta <guptap@codeaurora.org>
parent c7221f5f

drivers/iommu/arm-smmu.c

+18 −0
Original line number Diff line number Diff line
@@ -4143,11 +4143,29 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) 
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);

	int i;

	u32 reg;

	void __iomem *cb_base;

	u32 fsr;



	/* clear global FSR */

	reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);

	writel_relaxed(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);



	for (i = 0; i < smmu->num_context_banks; ++i) {

		cb_base = ARM_SMMU_CB(smmu, i);



		fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);

		if (fsr & FSR_FAULT) {

			writel_relaxed(fsr & FSR_FAULT, cb_base +

				       ARM_SMMU_CB_FSR);

			pr_err("CB %d, FSR 0x%x reset\n", i, fsr);

		}

	}



	/*

	 * Barrier required to ensure fault registers are cleared.

	 */

	wmb();



	/*

	 * Reset stream mapping groups: Initial values mark all SMRn as

	 * invalid and all S2CRn as bypass unless overridden.