Merge "ARM: dts: msm: add MSM PCIe bus driver device nodes for sdm855" into msm-4.14 (897affb4) · Commits · e / devices / android_kernel_xiaomi_sm6125

arch/arm64/boot/dts/qcom/sdm855-pcie.dtsi

0 → 100644

+564 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <dt-bindings/clock/qcom,gcc-sdm855.h>

		&soc {
		pcie0: qcom,pcie@1c00000 {
		compatible = "qcom,pci-msm";
		cell-index = <0>;

		reg = <0x1c00000 0x4000>,
		<0x1c04000 0x1000>,
		<0x60000000 0xf1d>,
		<0x60000f20 0xa8>,
		<0x60001000 0x1000>,
		<0x60100000 0x100000>,
		<0x60200000 0x100000>,
		<0x60300000 0x3d00000>;

		reg-names = "parf", "phy", "dm_core", "elbi",
		"iatu", "conf", "io", "bars";

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
		<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
		interrupt-parent = <&pcie0>;
		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
		20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
		36 37>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;
		interrupt-map = <0 0 0 0 &intc 0 141 0
		0 0 0 1 &intc 0 149 0
		0 0 0 2 &intc 0 150 0
		0 0 0 3 &intc 0 151 0
		0 0 0 4 &intc 0 152 0
		0 0 0 5 &intc 0 140 0
		0 0 0 6 &intc 0 768 0
		0 0 0 7 &intc 0 769 0
		0 0 0 8 &intc 0 770 0
		0 0 0 9 &intc 0 771 0
		0 0 0 10 &intc 0 772 0
		0 0 0 11 &intc 0 773 0
		0 0 0 12 &intc 0 774 0
		0 0 0 13 &intc 0 775 0
		0 0 0 14 &intc 0 776 0
		0 0 0 15 &intc 0 777 0
		0 0 0 16 &intc 0 778 0
		0 0 0 17 &intc 0 779 0
		0 0 0 18 &intc 0 780 0
		0 0 0 19 &intc 0 781 0
		0 0 0 20 &intc 0 782 0
		0 0 0 21 &intc 0 783 0
		0 0 0 22 &intc 0 784 0
		0 0 0 23 &intc 0 785 0
		0 0 0 24 &intc 0 786 0
		0 0 0 25 &intc 0 787 0
		0 0 0 26 &intc 0 788 0
		0 0 0 27 &intc 0 789 0
		0 0 0 28 &intc 0 790 0
		0 0 0 29 &intc 0 791 0
		0 0 0 30 &intc 0 792 0
		0 0 0 31 &intc 0 793 0
		0 0 0 32 &intc 0 794 0
		0 0 0 33 &intc 0 795 0
		0 0 0 34 &intc 0 796 0
		0 0 0 35 &intc 0 797 0
		0 0 0 36 &intc 0 798 0
		0 0 0 37 &intc 0 799 0>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c",
		"int_d", "int_global_int",
		"msi_0", "msi_1", "msi_2", "msi_3",
		"msi_4", "msi_5", "msi_6", "msi_7",
		"msi_8", "msi_9", "msi_10", "msi_11",
		"msi_12", "msi_13", "msi_14", "msi_15",
		"msi_16", "msi_17", "msi_18", "msi_19",
		"msi_20", "msi_21", "msi_22", "msi_23",
		"msi_24", "msi_25", "msi_26", "msi_27",
		"msi_28", "msi_29", "msi_30", "msi_31";

		qcom,phy-sequence = <0x02b4 0x03 0x0
		0x0840 0x03 0x0
		0x0094 0x08 0x0
		0x0154 0x32 0x0
		0x016c 0x08 0x0
		0x0058 0x0f 0x0
		0x00a4 0x42 0x0
		0x0110 0x24 0x0
		0x011c 0x03 0x0
		0x0118 0xb4 0x0
		0x010c 0x02 0x0
		0x01bc 0x11 0x0
		0x00bc 0x82 0x0
		0x00d4 0x03 0x0
		0x00d0 0x55 0x0
		0x00cc 0x55 0x0
		0x00b0 0x1a 0x0
		0x00ac 0x0a 0x0
		0x00c4 0x68 0x0
		0x00e0 0x02 0x0
		0x00dc 0xaa 0x0
		0x00d8 0xab 0x0
		0x00b8 0x34 0x0
		0x00b4 0x14 0x0
		0x0158 0x01 0x0
		0x0074 0x06 0x0
		0x007c 0x16 0x0
		0x0084 0x36 0x0
		0x0078 0x06 0x0
		0x0080 0x16 0x0
		0x0088 0x36 0x0
		0x01b0 0x1e 0x0
		0x01ac 0xb9 0x0
		0x01b8 0x18 0x0
		0x01b4 0x94 0x0
		0x0050 0x07 0x0
		0x0010 0x00 0x0
		0x001c 0x31 0x0
		0x0020 0x01 0x0
		0x0024 0xde 0x0
		0x0028 0x07 0x0
		0x0030 0x4c 0x0
		0x0034 0x06 0x0
		0x029c 0x12 0x0
		0x0284 0x05 0x0
		0x0c38 0x03 0x0
		0x0518 0x1c 0x0
		0x0524 0x14 0x0
		0x04ec 0x0e 0x0
		0x04f0 0x4a 0x0
		0x04f4 0x0f 0x0
		0x05b4 0x04 0x0
		0x0434 0x7f 0x0
		0x0444 0x70 0x0
		0x0510 0x17 0x0
		0x04d8 0x01 0x0
		0x0598 0xd4 0x0
		0x059c 0x54 0x0
		0x05a0 0xdb 0x0
		0x05a4 0x39 0x0
		0x05a8 0x31 0x0
		0x0584 0x24 0x0
		0x0588 0xe4 0x0
		0x058c 0xec 0x0
		0x0590 0x39 0x0
		0x0594 0x36 0x0
		0x0570 0xbd 0x0
		0x0574 0xbd 0x0
		0x0578 0x7f 0x0
		0x057c 0xfb 0x0
		0x0580 0x53 0x0
		0x04fc 0x00 0x0
		0x04f8 0xc0 0x0
		0x0414 0x04 0x0
		0x09a4 0x01 0x0
		0x0c90 0x00 0x0
		0x0c40 0x01 0x0
		0x0c48 0x01 0x0
		0x0c50 0x00 0x0
		0x0048 0x90 0x0
		0x0c1c 0xc1 0x0
		0x0988 0x66 0x0
		0x0998 0x08 0x0
		0x08dc 0x0d 0x0
		0x0800 0x00 0x0
		0x0844 0x03 0x0>;

		pinctrl-names = "default";
		pinctrl-0 = <&pcie0_clkreq_default
		&pcie0_perst_default
		&pcie0_wake_default>;

		perst-gpio = <&tlmm 35 0>;
		wake-gpio = <&tlmm 37 0>;

		gdsc-vdd-supply = <&pcie_0_gdsc>;
		vreg-1.8-supply = <&pm855l_l3>;
		vreg-0.9-supply = <&pm855_l5>;
		vreg-cx-supply = <&pm855l_s6_level>;

		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;
		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
		RPMH_REGULATOR_LEVEL_NOM 0>;

		qcom,l1-supported;
		qcom,l1ss-supported;
		qcom,aux-clk-sync;

		qcom,max-link-speed = <0x3>;

		qcom,ep-latency = <10>;

		qcom,slv-addr-space-size = <0x4000000>;

		qcom,phy-status-offset = <0x814>;

		qcom,boot-option = <0x1>;

		linux,pci-domain = <0>;

		qcom,msi-gicm-addr = <0x17a00040>;
		qcom,msi-gicm-base = <0x320>;

		qcom,pcie-phy-ver = <0x40>;
		qcom,use-19p2mhz-aux-clk;

		qcom,smmu-sid-base = <0x1d80>;

		iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
		<0x100 &apps_smmu 0x1d81 0x1>,
		<0x200 &apps_smmu 0x1d82 0x1>,
		<0x300 &apps_smmu 0x1d83 0x1>,
		<0x400 &apps_smmu 0x1d84 0x1>,
		<0x500 &apps_smmu 0x1d85 0x1>,
		<0x600 &apps_smmu 0x1d86 0x1>,
		<0x700 &apps_smmu 0x1d87 0x1>,
		<0x800 &apps_smmu 0x1d88 0x1>,
		<0x900 &apps_smmu 0x1d89 0x1>,
		<0xa00 &apps_smmu 0x1d8a 0x1>,
		<0xb00 &apps_smmu 0x1d8b 0x1>,
		<0xc00 &apps_smmu 0x1d8c 0x1>,
		<0xd00 &apps_smmu 0x1d8d 0x1>,
		<0xe00 &apps_smmu 0x1d8e 0x1>,
		<0xf00 &apps_smmu 0x1d8f 0x1>;

		qcom,msm-bus,name = "pcie0";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<45 512 0 0>,
		<45 512 500 800>;

		clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>,
		<&clock_gcc GCC_PCIE_0_AUX_CLK>,
		<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
		<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
		<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
		<&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
		<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
		<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
		<&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>,
		<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;

		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
		"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
		"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
		"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
		"pcie_tbu_clk", "pcie_phy_refgen_clk",
		"pcie_phy_aux_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>,
		<0>, <0>, <0>, <0>, <100000000>, <0>;

		resets = <&clock_gcc GCC_PCIE_0_BCR>,
		<&clock_gcc GCC_PCIE_0_PHY_BCR>;

		reset-names = "pcie_0_core_reset",
		"pcie_0_phy_reset";
		};

		pcie1: qcom,pcie@1c08000 {
		compatible = "qcom,pci-msm";
		cell-index = <1>;

		reg = <0x1c08000 0x4000>,
		<0x1c0c000 0x2000>,
		<0x40000000 0xf1d>,
		<0x40000f20 0xa8>,
		<0x40001000 0x1000>,
		<0x40100000 0x100000>,
		<0x40200000 0x100000>,
		<0x40300000 0x1fd00000>;

		reg-names = "parf", "phy", "dm_core", "elbi",
		"iatu", "conf", "io", "bars";

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
		<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
		interrupt-parent = <&pcie1>;
		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
		20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
		36 37>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;
		interrupt-map = <0 0 0 0 &intc 0 307 0
		0 0 0 1 &intc 0 434 0
		0 0 0 2 &intc 0 435 0
		0 0 0 3 &intc 0 438 0
		0 0 0 4 &intc 0 439 0
		0 0 0 5 &intc 0 306 0
		0 0 0 6 &intc 0 800 0
		0 0 0 7 &intc 0 801 0
		0 0 0 8 &intc 0 802 0
		0 0 0 9 &intc 0 803 0
		0 0 0 10 &intc 0 804 0
		0 0 0 11 &intc 0 805 0
		0 0 0 12 &intc 0 806 0
		0 0 0 13 &intc 0 807 0
		0 0 0 14 &intc 0 808 0
		0 0 0 15 &intc 0 809 0
		0 0 0 16 &intc 0 810 0
		0 0 0 17 &intc 0 811 0
		0 0 0 18 &intc 0 812 0
		0 0 0 19 &intc 0 813 0
		0 0 0 20 &intc 0 814 0
		0 0 0 21 &intc 0 815 0
		0 0 0 22 &intc 0 816 0
		0 0 0 23 &intc 0 817 0
		0 0 0 24 &intc 0 818 0
		0 0 0 25 &intc 0 819 0
		0 0 0 26 &intc 0 820 0
		0 0 0 27 &intc 0 821 0
		0 0 0 28 &intc 0 822 0
		0 0 0 29 &intc 0 823 0
		0 0 0 30 &intc 0 824 0
		0 0 0 31 &intc 0 825 0
		0 0 0 32 &intc 0 826 0
		0 0 0 33 &intc 0 827 0
		0 0 0 34 &intc 0 828 0
		0 0 0 35 &intc 0 829 0
		0 0 0 36 &intc 0 830 0
		0 0 0 37 &intc 0 831 0>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c",
		"int_d", "int_global_int",
		"msi_0", "msi_1", "msi_2", "msi_3",
		"msi_4", "msi_5", "msi_6", "msi_7",
		"msi_8", "msi_9", "msi_10", "msi_11",
		"msi_12", "msi_13", "msi_14", "msi_15",
		"msi_16", "msi_17", "msi_18", "msi_19",
		"msi_20", "msi_21", "msi_22", "msi_23",
		"msi_24", "msi_25", "msi_26", "msi_27",
		"msi_28", "msi_29", "msi_30", "msi_31";

		qcom,phy-sequence = <0x0a40 0x03 0x0
		0x0094 0x08 0x0
		0x0154 0x32 0x0
		0x016c 0x08 0x0
		0x0058 0x0f 0x0
		0x00a4 0x42 0x0
		0x0110 0x24 0x0
		0x011c 0x03 0x0
		0x0118 0xb4 0x0
		0x010c 0x02 0x0
		0x01bc 0x11 0x0
		0x00bc 0x82 0x0
		0x00d4 0x03 0x0
		0x00d0 0x55 0x0
		0x00cc 0x55 0x0
		0x00b0 0x1a 0x0
		0x00ac 0x0a 0x0
		0x00c4 0x68 0x0
		0x00e0 0x02 0x0
		0x00dc 0xaa 0x0
		0x00d8 0xab 0x0
		0x00b8 0x34 0x0
		0x00b4 0x14 0x0
		0x01bc 0x01 0x0
		0x0158 0x01 0x0
		0x0074 0x06 0x0
		0x007c 0x16 0x0
		0x0084 0x36 0x0
		0x0078 0x06 0x0
		0x0080 0x16 0x0
		0x0088 0x36 0x0
		0x01b0 0x1e 0x0
		0x01ac 0xb9 0x0
		0x01b8 0x18 0x0
		0x01b4 0x94 0x0
		0x0050 0x07 0x0
		0x0010 0x00 0x0
		0x001c 0x31 0x0
		0x0020 0x01 0x0
		0x0024 0xde 0x0
		0x0028 0x07 0x0
		0x0030 0x4c 0x0
		0x0034 0x06 0x0
		0x069c 0x12 0x0
		0x029c 0x12 0x0
		0x0284 0x05 0x0
		0x0684 0x05 0x0
		0x0e38 0x03 0x0
		0x051c 0x03 0x0
		0x091c 0x03 0x0
		0x0518 0x1c 0x0
		0x0918 0x1c 0x0
		0x0524 0x14 0x0
		0x0924 0x14 0x0
		0x08ec 0x0e 0x0
		0x04ec 0x0e 0x0
		0x08f0 0x4a 0x0
		0x04f0 0x4a 0x0
		0x08f4 0x0f 0x0
		0x04f4 0x0f 0x0
		0x05b4 0x04 0x0
		0x09b4 0x04 0x0
		0x0834 0x7f 0x0
		0x0434 0x7f 0x0
		0x0844 0x70 0x0
		0x0444 0x70 0x0
		0x0510 0x17 0x0
		0x0910 0x17 0x0
		0x08d8 0x01 0x0
		0x04d8 0x01 0x0
		0x0998 0xd4 0x0
		0x0598 0xd4 0x0
		0x099c 0x54 0x0
		0x059c 0x54 0x0
		0x05a0 0xdb 0x0
		0x09a0 0xdb 0x0
		0x05a4 0x39 0x0
		0x09a4 0x39 0x0
		0x05a8 0x31 0x0
		0x09a8 0x31 0x0
		0x0584 0x24 0x0
		0x0984 0x24 0x0
		0x0988 0xe4 0x0
		0x0588 0xe4 0x0
		0x098c 0xec 0x0
		0x058c 0xec 0x0
		0x0990 0x39 0x0
		0x0590 0x39 0x0
		0x0994 0x36 0x0
		0x0594 0x36 0x0
		0x0570 0xbd 0x0
		0x0970 0xbd 0x0
		0x0974 0xbd 0x0
		0x0574 0xbd 0x0
		0x0578 0x7f 0x0
		0x0978 0x7f 0x0
		0x097c 0xfb 0x0
		0x057c 0xfb 0x0
		0x0980 0x53 0x0
		0x0580 0x53 0x0
		0x08fc 0x00 0x0
		0x04fc 0x00 0x0
		0x08f8 0xc0 0x0
		0x04f8 0xc0 0x0
		0x0414 0x04 0x0
		0x0814 0x04 0x0
		0x0ba4 0x01 0x0
		0x0e90 0x00 0x0
		0x0e40 0x01 0x0
		0x0e48 0x01 0x0
		0x0e50 0x00 0x0
		0x0048 0x90 0x0
		0x0e1c 0xc1 0x0
		0x0b88 0x66 0x0
		0x0b98 0x08 0x0
		0x0adc 0x0d 0x0
		0x0a00 0x00 0x0
		0x0a44 0x03 0x0>;

		pinctrl-names = "default";
		pinctrl-0 = <&pcie1_clkreq_default
		&pcie1_perst_default
		&pcie1_wake_default>;

		perst-gpio = <&tlmm 102 0>;
		wake-gpio = <&tlmm 104 0>;

		gdsc-vdd-supply = <&pcie_1_gdsc>;
		vreg-1.8-supply = <&pm855l_l3>;
		vreg-0.9-supply = <&pm855_l5>;
		vreg-cx-supply = <&pm855l_s6_level>;

		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;
		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
		RPMH_REGULATOR_LEVEL_NOM 0>;

		qcom,l1-supported;
		qcom,l1ss-supported;
		qcom,aux-clk-sync;

		qcom,max-link-speed = <0x3>;

		qcom,ep-latency = <10>;

		qcom,slv-addr-space-size = <0x20000000>;

		qcom,phy-status-offset = <0xa14>;

		qcom,boot-option = <0x1>;

		linux,pci-domain = <1>;

		qcom,msi-gicm-addr = <0x17a00040>;
		qcom,msi-gicm-base = <0x340>;

		qcom,pcie-phy-ver = <0x40>;
		qcom,use-19p2mhz-aux-clk;

		qcom,smmu-sid-base = <0x1e00>;

		iommu-map = <0x0 &apps_smmu 0x1e10 0x1>,
		<0x100 &apps_smmu 0x1e11 0x1>,
		<0x200 &apps_smmu 0x1e12 0x1>,
		<0x300 &apps_smmu 0x1e13 0x1>,
		<0x400 &apps_smmu 0x1e14 0x1>,
		<0x500 &apps_smmu 0x1e15 0x1>,
		<0x600 &apps_smmu 0x1e16 0x1>,
		<0x700 &apps_smmu 0x1e17 0x1>,
		<0x800 &apps_smmu 0x1e18 0x1>,
		<0x900 &apps_smmu 0x1e19 0x1>,
		<0xa00 &apps_smmu 0x1e1a 0x1>,
		<0xb00 &apps_smmu 0x1e1b 0x1>,
		<0xc00 &apps_smmu 0x1e1c 0x1>,
		<0xd00 &apps_smmu 0x1e1d 0x1>,
		<0xe00 &apps_smmu 0x1e1e 0x1>,
		<0xf00 &apps_smmu 0x1e1f 0x1>;

		qcom,msm-bus,name = "pcie1";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<100 512 0 0>,
		<100 512 500 800>;

		clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>,
		<&clock_gcc GCC_PCIE_1_AUX_CLK>,
		<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
		<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
		<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
		<&clock_gcc GCC_PCIE_1_CLKREF_CLK>,
		<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
		<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
		<&clock_gcc GCC_PCIE1_PHY_REFGEN_CLK>,
		<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;

		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
		"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
		"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
		"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
		"pcie_tbu_clk", "pcie_phy_refgen_clk",
		"pcie_phy_aux_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>,
		<0>, <0>, <0>, <0>, <100000000>, <0>;

		resets = <&clock_gcc GCC_PCIE_1_BCR>,
		<&clock_gcc GCC_PCIE_1_PHY_BCR>;

		reset-names = "pcie_1_core_reset",
		"pcie_1_phy_reset";
		};
		};

arch/arm64/boot/dts/qcom/sdm855-pinctrl.dtsi

+82 −0

Original line number	Diff line number	Diff line
		@@ -283,6 +283,88 @@
		};
		};

		pcie0 {
		pcie0_clkreq_default: pcie0_clkreq_default {
		mux {
		pins = "gpio36";
		function = "pci_e0";
		};

		config {
		pins = "gpio36";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		pcie0_perst_default: pcie0_perst_default {
		mux {
		pins = "gpio35";
		function = "gpio";
		};

		config {
		pins = "gpio35";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		pcie0_wake_default: pcie0_wake_default {
		mux {
		pins = "gpio37";
		function = "gpio";
		};

		config {
		pins = "gpio37";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		pcie1 {
		pcie1_clkreq_default: pcie1_clkreq_default {
		mux {
		pins = "gpio103";
		function = "pci_e1";
		};

		config {
		pins = "gpio103";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		pcie1_perst_default: pcie1_perst_default {
		mux {
		pins = "gpio102";
		function = "gpio";
		};

		config {
		pins = "gpio102";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		pcie1_wake_default: pcie1_wake_default {
		mux {
		pins = "gpio104";
		function = "gpio";
		};

		config {
		pins = "gpio104";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		wil6210_refclk3_en_pin: wil6210_refclk3_en_pin {
		mux {
		pins = "gpio87";

arch/arm64/boot/dts/qcom/sdm855.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,8 @@
		aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
		pci-domain0 = &pcie0; /* PCIe0 domain */
		pci-domain1 = &pcie1; /* PCIe1 domain */
		};

		aliases {
		@@ -3229,6 +3231,7 @@
		#include "sdm855-regulator.dtsi"
		#include "sdm855-ion.dtsi"
		#include "sdm855-bus.dtsi"
		#include "sdm855-pcie.dtsi"
		#include "sdm855-smp2p.dtsi"
		#include "sdm855-coresight.dtsi"
		#include "msm-arm-smmu-sdm855.dtsi"