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Commit b89ea9bb authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes Ibe433b66,I64d6c928,I689f3a39,Id68a8fa3 into msm-4.14 

* changes:
  defconfig: sdm855: enable QTI crypto driver
  ARM: dts: msm: add crypto devices for sdm855
  crypto: qcedev: change to use sg_init_one
  crypto: msm: add changes about no clock support
parents 771ea9db ab0003d0

Documentation/devicetree/bindings/crypto/msm/qcedev.txt

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Optional properties: 
  - qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target. Default value is 1 if not specified.

  - qcom,smmu-s1-enable : Boolean flag to enable SMMU stage 1 translation.

  - iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.

  - qcom,no-clock-support : indicates clocks are not handled by hlos crypto driver.



Example:

Documentation/devicetree/bindings/crypto/msm/qcrypto.txt

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ Optional properties: 


  - qcom,smmu-s1-enable : Boolean flag to bypass SMMU stage 1 translation.

  - iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.

  - qcom,no-clock-support : indicates clocks are not handled by hlos crypto driver.



Example:

arch/arm64/boot/dts/qcom/sdm855.dtsi

+53 −0
Original line number Diff line number Diff line
@@ -2500,6 +2500,59 @@ 
		clock-names = "iface";

	};



	qcom_cedev: qcedev@1de0000 {

		compatible = "qcom,qcedev";

		reg = <0x1de0000 0x20000>,

			<0x1dc4000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 272 0>;

		qcom,bam-pipe-pair = <3>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,bam-ee = <0>;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<125 512 0 0>,

				<125 512 393600 393600>;

		qcom,smmu-s1-enable;

		qcom,no-clock-support;

		iommus = <&apps_smmu 0x0506 0x0011>,

			 <&apps_smmu 0x0516 0x0011>;

	};



	qcom_crypto: qcrypto@1de0000 {

		compatible = "qcom,qcrypto";

		reg = <0x1de0000 0x20000>,

			 <0x1dc4000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 272 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,bam-ee = <0>;

		qcom,ce-hw-shared;

		qcom,clk-mgmt-sus-res;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<125 512 0 0>,

			<125 512 393600 393600>;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,use-sw-aead-algo;

		qcom,use-sw-hmac-algo;

		qcom,smmu-s1-enable;

		qcom,no-clock-support;

		iommus = <&apps_smmu 0x0504 0x0011>,

			 <&apps_smmu 0x0514 0x0011>;

	};



	mem_dump {

		compatible = "qcom,mem-dump";

		memory-region = <&dump_mem>;

arch/arm64/configs/sdm855-perf_defconfig

+3 −1
Original line number Diff line number Diff line
@@ -576,7 +576,9 @@ CONFIG_CRYPTO_XCBC=y 
CONFIG_CRYPTO_MD4=y

CONFIG_CRYPTO_TWOFISH=y

CONFIG_CRYPTO_ANSI_CPRNG=y

CONFIG_CRYPTO_DEV_QCE=y

CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y

CONFIG_CRYPTO_DEV_QCRYPTO=y

CONFIG_CRYPTO_DEV_QCEDEV=y

CONFIG_ARM64_CRYPTO=y

CONFIG_CRYPTO_SHA1_ARM64_CE=y

CONFIG_CRYPTO_SHA2_ARM64_CE=y

arch/arm64/configs/sdm855_defconfig

+3 −1
Original line number Diff line number Diff line
@@ -653,7 +653,9 @@ CONFIG_CRYPTO_XCBC=y 
CONFIG_CRYPTO_MD4=y

CONFIG_CRYPTO_TWOFISH=y

CONFIG_CRYPTO_ANSI_CPRNG=y

CONFIG_CRYPTO_DEV_QCE=y

CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y

CONFIG_CRYPTO_DEV_QCRYPTO=y

CONFIG_CRYPTO_DEV_QCEDEV=y

CONFIG_ARM64_CRYPTO=y

CONFIG_CRYPTO_SHA1_ARM64_CE=y

CONFIG_CRYPTO_SHA2_ARM64_CE=y