Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 61e309f3 authored by Doug Anderson's avatar Doug Anderson Committed by Heiko Stuebner
Browse files

clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_pre 



We'd like to be able to call clk_set_rate() on aclk_cpu (a gate) at
bootup.  In order for this to have any effect we need its parent
(aclk_cpu_pre) to percolate the rate change to _its_ parent
(aclk_cpu_src).  Add CLK_SET_RATE_PARENT to make this happen.

Signed-off-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent de7d6c3e

drivers/clk/rockchip/clk-rk3288.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -279,7 +279,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
			RK3288_CLKGATE_CON(0), 11, GFLAGS),

			RK3288_CLKGATE_CON(0), 11, GFLAGS),

	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,

	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,

			RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),

			RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),

	DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,

	DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,

			RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),

			RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),

	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,

	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,

			RK3288_CLKGATE_CON(0), 3, GFLAGS),

			RK3288_CLKGATE_CON(0), 3, GFLAGS),