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Commit 328e4eeb authored by Ritesh Kumar's avatar Ritesh Kumar Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: update PHY configuration to support cphy 



Add support to read cphy boolean flag from panel dtsi
and configure DSI PHY registers accordingly. Update
bit/byte clock calculation according to cphy specifications.
Update clock parents so that the relevant divider blocks
are configured to support cphy.

Change-Id: Iaca61eec01a488657b086f59910c52f8c79e26a4
Signed-off-by: default avatarChandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent 688f129a

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+1 −0
Original line number Diff line number Diff line
@@ -497,6 +497,7 @@ Optional properties: 
- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel

			   for any commands that we send.

- qcom,mdss-dsi-force-clock-lane-hs:	Boolean to force dsi clock lanes to HS mode always.

- qcom,panel-cphy-mode:			Boolean to specify whether panel is using cphy.



- qcom,compression-mode:		Select compression mode for panel.

					"fbc" - frame buffer compression

drivers/gpu/drm/msm/dsi-staging/dsi_clk.h

+6 −2
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -117,11 +117,13 @@ struct dsi_link_lp_clk_info { 
/**

 * struct link_clk_freq - Clock frequency information for Link clocks

 * @byte_clk_rate:   Frequency of DSI byte_clk in KHz.

 * @byte_intf_clk_rate:   Frequency of DSI byte_intf_clk in KHz.

 * @pixel_clk_rate:  Frequency of DSI pixel_clk in KHz.

 * @esc_clk_rate:    Frequency of DSI escape clock in KHz.

 */

struct link_clk_freq {

	u32 byte_clk_rate;

	u32 byte_intf_clk_rate;

	u32 pix_clk_rate;

	u32 esc_clk_rate;

};
@@ -306,10 +308,12 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index); 
 * dsi_clk_set_byte_clk_rate() - set frequency for byte clock

 * @client:       DSI clock client pointer.

 * @byte_clk: Pixel clock rate in Hz.

 * @byte_intf_clk: Byte interface clock rate in Hz.

 * @index:      Index of the DSI controller.

 * return: error code in case of failure or 0 for success.

 */

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index);

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,

				u64 byte_intf_clk, u32 index);



/**

 * dsi_clk_update_parent() - update parent clocks for specified clock

drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c

+9 −8
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -139,15 +139,16 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index) 
 * dsi_clk_set_byte_clk_rate() - set frequency for byte clock

 * @client:	DSI clock client pointer.

 * @byte_clk:	Byte clock rate in Hz.

 * @byte_intf_clk: Byte interface clock rate in Hz.

 * @index:	Index of the DSI controller.

 * return: error code in case of failure or 0 for success.

 */

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index)

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,

					u64 byte_intf_clk, u32 index)

{

	int rc = 0;

	struct dsi_clk_client_info *c = client;

	struct dsi_clk_mngr *mngr;

	u64 byte_intf_rate;



	mngr = c->mngr;

	rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_clk, byte_clk);
@@ -157,12 +158,14 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) 
		mngr->link_clks[index].freq.byte_clk_rate = byte_clk;



	if (mngr->link_clks[index].hs_clks.byte_intf_clk) {

		byte_intf_rate = mngr->link_clks[index].freq.byte_clk_rate / 2;

		rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_intf_clk,

				  byte_intf_rate);

							byte_intf_clk);

		if (rc)

			pr_err("failed to set clk rate for byte intf clk=%d\n",

			       rc);

		else

			mngr->link_clks[index].freq.byte_intf_clk_rate

							= byte_intf_clk;

	}



	return rc;
@@ -371,12 +374,10 @@ static int dsi_link_hs_clk_set_rate(struct dsi_link_hs_clk_info *link_hs_clks, 


	/*

	 * If byte_intf_clk is present, set rate for that too.

	 * For DPHY: byte_intf_clk_rate = byte_clk_rate / 2

	 * todo: this needs to be revisited when support for CPHY is added

	 */

	if (link_hs_clks->byte_intf_clk) {

		rc = clk_set_rate(link_hs_clks->byte_intf_clk,

			(l_clks->freq.byte_clk_rate / 2));

				l_clks->freq.byte_intf_clk_rate);

		if (rc) {

			pr_err("set_rate failed for byte_intf_clk rc = %d\n",

				rc);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+30 −9
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -830,10 +830,11 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	u32 bpp;

	u64 refresh_rate = TICKS_IN_MICRO_SECOND;

	u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,

	    byte_clk_rate;

				byte_clk_rate, byte_intf_clk_rate;

	struct dsi_host_common_cfg *host_cfg = &config->common_config;

	struct dsi_split_link_config *split_link = &host_cfg->split_link;

	struct dsi_mode_info *timing = &config->video_timing;

	u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */



	/* Get bits per pxl in desitnation format */

	bpp = dsi_ctrl_pixel_format_to_bpp(host_cfg->dst_format);
@@ -865,23 +866,43 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
		bit_rate = h_period * v_period * refresh_rate * bpp;

	} else {

		bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;

		if (host_cfg->phy_type == DSI_PHY_TYPE_CPHY) {

			bit_rate *= bits_per_symbol;

			do_div(bit_rate, num_of_symbols);

		}

	}



	bit_rate_per_lane = bit_rate;

	do_div(bit_rate_per_lane, num_of_lanes);

	pclk_rate = bit_rate;

	do_div(pclk_rate, bpp);

	if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {

		bit_rate_per_lane = bit_rate;

		do_div(bit_rate_per_lane, num_of_lanes);

		byte_clk_rate = bit_rate_per_lane;

		do_div(byte_clk_rate, 8);

		byte_intf_clk_rate = byte_clk_rate;

		do_div(byte_intf_clk_rate, 2);

		config->bit_clk_rate_hz = byte_clk_rate * 8;

	} else {

		do_div(bit_rate, bits_per_symbol);

		bit_rate *= num_of_symbols;

		bit_rate_per_lane = bit_rate;

		do_div(bit_rate_per_lane, num_of_lanes);

		byte_clk_rate = bit_rate_per_lane;

		do_div(byte_clk_rate, 7);

		/* For CPHY, byte_intf_clk is same as byte_clk */

		byte_intf_clk_rate = byte_clk_rate;

		config->bit_clk_rate_hz = byte_clk_rate * 7;

	}

	pr_debug("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",

		 bit_rate, bit_rate_per_lane);

	pr_debug("byte_clk_rate = %llu, pclk_rate = %llu\n",

		  byte_clk_rate, pclk_rate);

	pr_debug("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",

		  byte_clk_rate, byte_intf_clk_rate);

	pr_debug("pclk_rate = %llu\n", pclk_rate);



	dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;

	dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;

	dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;

	dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;

	config->bit_clk_rate_hz = dsi_ctrl->clk_freq.byte_clk_rate * 8;



	rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,

					dsi_ctrl->cell_index);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c

+4 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -127,6 +127,9 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl, 


	DSI_W32(ctrl, DSI_CTRL, reg_value);



	if (cfg->phy_type == DSI_PHY_TYPE_CPHY)

		DSI_W32(ctrl, DSI_CPHY_MODE_CTRL, BIT(0));



	if (ctrl->phy_isolation_enabled)

		DSI_W32(ctrl, DSI_DEBUG_CTRL, BIT(28));

	pr_debug("[DSI_%d]Host configuration complete\n", ctrl->index);