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Commit 688f129a authored by Ritesh Kumar's avatar Ritesh Kumar Committed by Gerrit - the friendly Code Review server
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clk: qcom: mdss: add additional dividers for CPHY support 



Panels supporting Cphy use a specific divider
blocks. Add additional divider blocks for byte
and pixel clock output to support DSI CPHY.

Change-Id: I74b3ee2bdd22ae8fa20567fe837e03915537c4fb
Signed-off-by: default avatarChandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent 91aa9b06

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+275 −57
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -187,6 +187,7 @@ 
/* Register Offsets from PHY base address */

#define PHY_CMN_CLK_CFG0	0x010

#define PHY_CMN_CLK_CFG1	0x014

#define PHY_CMN_GLBL_CTRL	0x018

#define PHY_CMN_RBUF_CTRL	0x01C

#define PHY_CMN_CTRL_0		0x024

#define PHY_CMN_CTRL_3		0x030
@@ -248,6 +249,7 @@ struct dsi_pll_7nm { 
	struct mdss_pll_resources *rsc;

	struct dsi_pll_config pll_configuration;

	struct dsi_pll_regs reg_setup;

	bool cphy_enabled;

};



static inline bool dsi_pll_7nm_is_hw_revision_v1(
@@ -381,7 +383,7 @@ static inline int phy_reg_update_bits(void *context, unsigned int reg, 
	return rc;

}



static inline int pclk_mux_read_sel(void *context, unsigned int reg,

static int pclk_mux_read_sel(void *context, unsigned int reg,

					unsigned int *val)

{

	int rc = 0;
@@ -413,11 +415,12 @@ static inline int pclk_mux_write_sel_sub(struct mdss_pll_resources *rsc, 
	return rc;

}



static inline int pclk_mux_write_sel(void *context, unsigned int reg,

static int pclk_mux_write_sel(void *context, unsigned int reg,

					unsigned int val)

{

	int rc = 0;

	struct mdss_pll_resources *rsc = context;

	struct dsi_pll_7nm *pll = rsc->priv;



	rc = mdss_pll_resource_enable(rsc, true);

	if (rc) {
@@ -425,6 +428,61 @@ static inline int pclk_mux_write_sel(void *context, unsigned int reg, 
		return rc;

	}



	if (pll->cphy_enabled)

		WARN_ON("PHY is in CPHY mode. PLL config is incorrect\n");

	rc = pclk_mux_write_sel_sub(rsc, reg, val);

	if (!rc && rsc->slave)

		rc = pclk_mux_write_sel_sub(rsc->slave, reg, val);



	(void)mdss_pll_resource_enable(rsc, false);



	/*

	 * cache the current parent index for cases where parent

	 * is not changing but rate is changing. In that case

	 * clock framework won't call parent_set and hence dsiclk_sel

	 * bit won't be programmed. e.g. dfps update use case.

	 */

	rsc->cached_cfg1 = val;



	return rc;

}



static int cphy_pclk_mux_read_sel(void *context, unsigned int reg,

					unsigned int *val)

{

	int rc = 0;

	struct mdss_pll_resources *rsc = context;



	rc = mdss_pll_resource_enable(rsc, true);

	if (rc) {

		pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);

		return rc;

	}



	*val = (MDSS_PLL_REG_R(rsc->phy_base, reg) & 0x3);



	(void)mdss_pll_resource_enable(rsc, false);

	return rc;

}



static int cphy_pclk_mux_write_sel(void *context, unsigned int reg,

					unsigned int val)

{

	int rc = 0;

	struct mdss_pll_resources *rsc = context;

	struct dsi_pll_7nm *pll = rsc->priv;



	rc = mdss_pll_resource_enable(rsc, true);

	if (rc) {

		pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);

		return rc;

	}



	if (!pll->cphy_enabled)

		WARN_ON("PHY-> not in CPHY mode. PLL config is incorrect\n");

	/* For Cphy configuration, val should always be 3 */

	val = 3;



	rc = pclk_mux_write_sel_sub(rsc, reg, val);

	if (!rc && rsc->slave)

		rc = pclk_mux_write_sel_sub(rsc->slave, reg, val);
@@ -796,6 +854,14 @@ static void dsi_pll_init_val(struct mdss_pll_resources *rsc) 


}



static void dsi_pll_detect_phy_mode(struct dsi_pll_7nm *pll,

			   struct mdss_pll_resources *rsc)

{

	u32 reg_val = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_GLBL_CTRL);



	pll->cphy_enabled = (reg_val & BIT(6)) ? true : false;

}



static void dsi_pll_commit(struct dsi_pll_7nm *pll,

			   struct mdss_pll_resources *rsc)

{
@@ -813,7 +879,8 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, 
		       reg->frac_div_start_high);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_1, 0x40);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_DELAY, 0x06);

	MDSS_PLL_REG_W(pll_base, PLL_CMODE_1, 0x10);

	MDSS_PLL_REG_W(pll_base, PLL_CMODE_1,

				pll->cphy_enabled ? 0x00 : 0x10);

	MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS_1,

			reg->pll_clock_inverters);

}
@@ -854,6 +921,8 @@ static int vco_7nm_set_rate(struct clk_hw *hw, unsigned long rate, 


	dsi_pll_init_val(rsc);



	dsi_pll_detect_phy_mode(pll, rsc);



	dsi_pll_setup_config(pll, rsc);



	dsi_pll_calc_dec_frac(pll, rsc);
@@ -949,11 +1018,16 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) 
{

	int rc;

	struct mdss_pll_resources *rsc = vco->priv;

	struct dsi_pll_7nm *pll = rsc->priv;



	dsi_pll_enable_pll_bias(rsc);

	if (rsc->slave)

		dsi_pll_enable_pll_bias(rsc->slave);



	/* For Cphy configuration, pclk_mux is always set to 3 divider */

	if (pll->cphy_enabled)

		rsc->cached_cfg1 |= 0x3;



	phy_reg_update_bits_sub(rsc, PHY_CMN_CLK_CFG1, 0x03, rsc->cached_cfg1);

	if (rsc->slave)

		phy_reg_update_bits_sub(rsc->slave, PHY_CMN_CLK_CFG1,
@@ -1334,6 +1408,11 @@ static struct regmap_bus pclk_src_mux_regmap_bus = { 
	.reg_write = pclk_mux_write_sel,

};



static struct regmap_bus cphy_pclk_src_mux_regmap_bus = {

	.reg_read = cphy_pclk_mux_read_sel,

	.reg_write = cphy_pclk_mux_write_sel,

};



static struct regmap_bus pclk_src_regmap_bus = {

	.reg_write = pixel_clk_set_div,

	.reg_read = pixel_clk_get_div,
@@ -1371,42 +1450,41 @@ static struct regmap_bus mdss_mux_regmap_bus = { 
 *                  |  DIV(1,2,4,8) |

 *                  +-------+-------+

 *                          |

 *                          +-----------------------------+--------+

 *                          +-----------------------------+-------+---------------+

 *                          |                             |       |               |

 *                  +-------v-------+                     |       |               |

 *                  |  bitclk_src   |                     |       |               |

 *                  |  DIV(1..15)   |                     |       |               |

 *                  +-------+-------+                     |       |               |

 *                          |                             |       |               |

 *            +-------------v+---------+---------+        |       |               |

 *            |              |         |         |        |       |               |

 *      +-----v-----+  +-----v-----+   |  +------v------+ | +-----v------+  +-----v------+

 *      |byteclk_src|  |byteclk_src|   |  |post_bit_div | | |post_vco_div|  |post_vco_div|

 *      |  DIV(8)   |  |  DIV(7)   |   |  |   DIV (2)   | | |   DIV(4)   |  |  DIV(3.5)  |

 *      +-----+-----+  +-----+-----+   |  +------+------+ | +-----+------+  +------+-----+

 *            |              |         |         |        |       |                |

 *Shadow Path |          CPHY Path     |         |        |       |           +----v

 *     +      |              |         +------+  |        |   +---+           |

 *     +---+  |        +-----+                |  |        |   |               |

 *         |  |        |                    +-v--v----v---v---+      +--------v--------+

 *     +---v--v--------v---+                 \  pclk_src_mux /        \ cphy_pclk_src /

 *      \   byteclk_mux   /                   \             /          \     mux     /

 *       \               /                     +-----+-----+            +-----+-----+

 *        +------+------+                            |      Shadow Path       |

 *               |                                   |           +            |

 *               v                             +-----v------+    |     +------v------+

 *         dsi_byte_clk                        |  pclk_src  |    |     |cphy_pclk_src|

 *                                             | DIV(1..15) |    |     |  DIV(1..15) |

 *                                             +-----+------+    |     +------+------+

 *                                                   |           |            |

 *                  +-------v-------+                     |        |

 *                  |  bitclk_src   |                     |        |

 *                  |  DIV(1..15)   |                     |        |

 *                  +-------+-------+                     |        |

 *                                                   |           |        CPHY Path

 *                                                   |           |            |

 *                          +----------+---------+        |        |

 *   Shadow Path            |          |         |        |        |

 *       +          +-------v-------+  |  +------v------+ | +------v-------+

 *       |          |  byteclk_src  |  |  |post_bit_div | | |post_vco_div  |

 *       |          |  DIV(8)       |  |  |DIV (2)      | | |DIV(4)        |

 *       |          +-------+-------+  |  +------+------+ | +------+-------+

 *       |                  |          |         |      | |        |

 *       |                  |          |         +------+ |        |

 *       |                  |          +-------------+  | |   +----+

 *       |         +--------+                        |  | |   |

 *       |         |                               +-v--v-v---v------+

 *     +-v---------v----+                           \  pclk_src_mux /

 *     \  byteclk_mux /                              \             /

 *      \            /                                +-----+-----+

 *       +----+-----+                                       |        Shadow Path

 *            |                                             |             +

 *            v                                       +-----v------+      |

 *       dsi_byte_clk                                 |  pclk_src  |      |

 *                                                    | DIV(1..15) |      |

 *                                                    +-----+------+      |

 *                                                          |             |

 *                                                          |             |

 *                                                          +--------+    |

 *                                                                   |    |

 *                                                               +---v----v----+

 *                                                   +-------+   |    +-------+

 *                                                           |   |    |

 *                                                       +---v---v----v------+

 *                                                        \     pclk_mux    /

 *                                                                 \         /

 *                                                                  +---+---+

 *                                                                      |

 *                                                          +------+------+

 *                                                                 |

 *                                                                 v

 *                                                              dsi_pclk
@@ -1523,6 +1601,30 @@ static struct clk_fixed_factor dsi1pll_post_vco_div = { 
	},

};



static struct clk_fixed_factor dsi0pll_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,

	.hw.init = &(struct clk_init_data){

		.name = "dsi0pll_post_vco_div3_5",

		.parent_names = (const char *[]){"dsi0pll_pll_out_div"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,

	.hw.init = &(struct clk_init_data){

		.name = "dsi1pll_post_vco_div3_5",

		.parent_names = (const char *[]){"dsi1pll_pll_out_div"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi0pll_byteclk_src = {

	.div = 8,

	.mult = 1,
@@ -1547,6 +1649,30 @@ static struct clk_fixed_factor dsi1pll_byteclk_src = { 
	},

};



static struct clk_fixed_factor dsi0pll_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi0pll_cphy_byteclk_src",

		.parent_names = (const char *[]){"dsi0pll_bitclk_src"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi1pll_cphy_byteclk_src",

		.parent_names = (const char *[]){"dsi1pll_bitclk_src"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi0pll_post_bit_div = {

	.div = 2,

	.mult = 1,
@@ -1577,9 +1703,11 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { 
	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0_phy_pll_out_byteclk",

			.parent_names = (const char *[]){"dsi0pll_byteclk_src"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.parent_names = (const char *[]){"dsi0pll_byteclk_src",

				"dsi0pll_cphy_byteclk_src"},

			.num_parents = 2,

			.flags = (CLK_GET_RATE_NOCACHE |

				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,

		},

	},
@@ -1591,9 +1719,11 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { 
	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1_phy_pll_out_byteclk",

			.parent_names = (const char *[]){"dsi1pll_byteclk_src"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.parent_names = (const char *[]){"dsi1pll_byteclk_src",

				"dsi1pll_cphy_byteclk_src"},

			.num_parents = 2,

			.flags = (CLK_GET_RATE_NOCACHE |

				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,

		},

	},
@@ -1617,6 +1747,22 @@ static struct clk_regmap_mux dsi0pll_pclk_src_mux = { 
	},

};



static struct clk_regmap_mux dsi0pll_cphy_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,

	.width = 2,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_cphy_pclk_src_mux",

			.parent_names =

				(const char *[]){"dsi0pll_post_vco_div3_5"},

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};



static struct clk_regmap_mux dsi1pll_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,
@@ -1635,6 +1781,22 @@ static struct clk_regmap_mux dsi1pll_pclk_src_mux = { 
	},

};



static struct clk_regmap_mux dsi1pll_cphy_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,

	.width = 2,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_cphy_pclk_src_mux",

			.parent_names =

				(const char *[]){"dsi1pll_post_vco_div3_5"},

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};



static struct clk_regmap_div dsi0pll_pclk_src = {

	.shift = 0,

	.width = 4,
@@ -1650,6 +1812,21 @@ static struct clk_regmap_div dsi0pll_pclk_src = { 
	},

};



static struct clk_regmap_div dsi0pll_cphy_pclk_src = {

	.shift = 0,

	.width = 4,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_cphy_pclk_src",

			.parent_names = (const char *[]){

					"dsi0pll_cphy_pclk_src_mux"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.ops = &clk_regmap_div_ops,

		},

	},

};



static struct clk_regmap_div dsi1pll_pclk_src = {

	.shift = 0,

	.width = 4,
@@ -1665,15 +1842,32 @@ static struct clk_regmap_div dsi1pll_pclk_src = { 
	},

};



static struct clk_regmap_div dsi1pll_cphy_pclk_src = {

	.shift = 0,

	.width = 4,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_cphy_pclk_src",

			.parent_names = (const char *[]){

					"dsi1pll_cphy_pclk_src_mux"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.ops = &clk_regmap_div_ops,

		},

	},

};



static struct clk_regmap_mux dsi0pll_pclk_mux = {

	.shift = 0,

	.width = 1,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi0pll_pclk_src"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.parent_names = (const char *[]){"dsi0pll_pclk_src",

					"dsi0pll_cphy_pclk_src"},

			.num_parents = 2,

			.flags = (CLK_GET_RATE_NOCACHE |

				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,

		},

	},
@@ -1685,9 +1879,11 @@ static struct clk_regmap_mux dsi1pll_pclk_mux = { 
	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi1pll_pclk_src"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.parent_names = (const char *[]){"dsi1pll_pclk_src",

					"dsi1pll_cphy_pclk_src"},

			.num_parents = 2,

			.flags = (CLK_GET_RATE_NOCACHE |

				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,

		},

	},
@@ -1698,22 +1894,30 @@ static struct clk_hw *mdss_dsi_pllcc_7nm[] = { 
	[PLL_OUT_DIV_0_CLK] = &dsi0pll_pll_out_div.clkr.hw,

	[BITCLK_SRC_0_CLK] = &dsi0pll_bitclk_src.clkr.hw,

	[BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw,

	[CPHY_BYTECLK_SRC_0_CLK] = &dsi0pll_cphy_byteclk_src.hw,

	[POST_BIT_DIV_0_CLK] = &dsi0pll_post_bit_div.hw,

	[POST_VCO_DIV_0_CLK] = &dsi0pll_post_vco_div.hw,

	[POST_VCO_DIV3_5_0_CLK] = &dsi0pll_post_vco_div3_5.hw,

	[BYTECLK_MUX_0_CLK] = &dsi0pll_byteclk_mux.clkr.hw,

	[PCLK_SRC_MUX_0_CLK] = &dsi0pll_pclk_src_mux.clkr.hw,

	[PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,

	[PCLK_MUX_0_CLK] = &dsi0pll_pclk_mux.clkr.hw,

	[CPHY_PCLK_SRC_MUX_0_CLK] = &dsi0pll_cphy_pclk_src_mux.clkr.hw,

	[CPHY_PCLK_SRC_0_CLK] = &dsi0pll_cphy_pclk_src.clkr.hw,

	[VCO_CLK_1] = &dsi1pll_vco_clk.hw,

	[PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw,

	[BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw,

	[BYTECLK_SRC_1_CLK] = &dsi1pll_byteclk_src.hw,

	[CPHY_BYTECLK_SRC_1_CLK] = &dsi1pll_cphy_byteclk_src.hw,

	[POST_BIT_DIV_1_CLK] = &dsi1pll_post_bit_div.hw,

	[POST_VCO_DIV_1_CLK] = &dsi1pll_post_vco_div.hw,

	[POST_VCO_DIV3_5_1_CLK] = &dsi1pll_post_vco_div3_5.hw,

	[BYTECLK_MUX_1_CLK] = &dsi1pll_byteclk_mux.clkr.hw,

	[PCLK_SRC_MUX_1_CLK] = &dsi1pll_pclk_src_mux.clkr.hw,

	[PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw,

	[PCLK_MUX_1_CLK] = &dsi1pll_pclk_mux.clkr.hw,

	[CPHY_PCLK_SRC_MUX_1_CLK] = &dsi1pll_cphy_pclk_src_mux.clkr.hw,

	[CPHY_PCLK_SRC_1_CLK] = &dsi1pll_cphy_pclk_src.clkr.hw,

};



int dsi_pll_clock_register_7nm(struct platform_device *pdev,
@@ -1770,6 +1974,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
		rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,

				pll_res, &dsi_pll_7nm_config);

		dsi0pll_pclk_src.clkr.regmap = rmap;

		dsi0pll_cphy_pclk_src.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);
@@ -1778,12 +1983,18 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
		rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);

		dsi0pll_pclk_src_mux.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev,

					&cphy_pclk_src_mux_regmap_bus,

					pll_res, &dsi_pll_7nm_config);

		dsi0pll_cphy_pclk_src_mux.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);

		dsi0pll_byteclk_mux.clkr.regmap = rmap;



		dsi0pll_vco_clk.priv = pll_res;

		for (i = VCO_CLK_0; i <= PCLK_MUX_0_CLK; i++) {

		for (i = VCO_CLK_0; i <= CPHY_PCLK_SRC_0_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_7nm[i]);

			if (IS_ERR(clk)) {
@@ -1812,6 +2023,7 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
		rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,

				pll_res, &dsi_pll_7nm_config);

		dsi1pll_pclk_src.clkr.regmap = rmap;

		dsi1pll_cphy_pclk_src.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);
@@ -1820,12 +2032,18 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev, 
		rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);

		dsi1pll_pclk_src_mux.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev,

					&cphy_pclk_src_mux_regmap_bus,

					pll_res, &dsi_pll_7nm_config);

		dsi1pll_cphy_pclk_src_mux.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_7nm_config);

		dsi1pll_byteclk_mux.clkr.regmap = rmap;

		dsi1pll_vco_clk.priv = pll_res;



		for (i = VCO_CLK_1; i <= PCLK_MUX_1_CLK; i++) {

		for (i = VCO_CLK_1; i <= CPHY_PCLK_SRC_1_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_7nm[i]);

			if (IS_ERR(clk)) {

include/dt-bindings/clock/mdss-10nm-pll-clk.h

+39 −27
Original line number Diff line number Diff line 


/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -26,32 +26,44 @@ 
#define PCLK_SRC_MUX_0_CLK	7

#define PCLK_SRC_0_CLK		8

#define PCLK_MUX_0_CLK		9

#define SHADOW_VCO_CLK_0		10

#define SHADOW_PLL_OUT_DIV_0_CLK	11

#define SHADOW_BITCLK_SRC_0_CLK		12

#define SHADOW_BYTECLK_SRC_0_CLK	13

#define SHADOW_POST_BIT_DIV_0_CLK	14

#define SHADOW_POST_VCO_DIV_0_CLK	15

#define SHADOW_PCLK_SRC_MUX_0_CLK	16

#define SHADOW_PCLK_SRC_0_CLK		17

#define VCO_CLK_1		18

#define PLL_OUT_DIV_1_CLK	19

#define BITCLK_SRC_1_CLK	20

#define BYTECLK_SRC_1_CLK	21

#define POST_BIT_DIV_1_CLK	22

#define POST_VCO_DIV_1_CLK	23

#define BYTECLK_MUX_1_CLK	24

#define PCLK_SRC_MUX_1_CLK	25

#define PCLK_SRC_1_CLK		26

#define PCLK_MUX_1_CLK		27

#define SHADOW_VCO_CLK_1		28

#define SHADOW_PLL_OUT_DIV_1_CLK	29

#define SHADOW_BITCLK_SRC_1_CLK		30

#define SHADOW_BYTECLK_SRC_1_CLK	31

#define SHADOW_POST_BIT_DIV_1_CLK	32

#define SHADOW_POST_VCO_DIV_1_CLK	33

#define SHADOW_PCLK_SRC_MUX_1_CLK	34

#define SHADOW_PCLK_SRC_1_CLK		35

/* CPHY clocks for DSI-0 PLL */

#define CPHY_BYTECLK_SRC_0_CLK	10

#define POST_VCO_DIV3_5_0_CLK	11

#define CPHY_PCLK_SRC_MUX_0_CLK	12

#define CPHY_PCLK_SRC_0_CLK	13



#define SHADOW_VCO_CLK_0		14

#define SHADOW_PLL_OUT_DIV_0_CLK	15

#define SHADOW_BITCLK_SRC_0_CLK		16

#define SHADOW_BYTECLK_SRC_0_CLK	17

#define SHADOW_POST_BIT_DIV_0_CLK	18

#define SHADOW_POST_VCO_DIV_0_CLK	19

#define SHADOW_PCLK_SRC_MUX_0_CLK	20

#define SHADOW_PCLK_SRC_0_CLK		21

#define VCO_CLK_1		22

#define PLL_OUT_DIV_1_CLK	23

#define BITCLK_SRC_1_CLK	24

#define BYTECLK_SRC_1_CLK	25

#define POST_BIT_DIV_1_CLK	26

#define POST_VCO_DIV_1_CLK	27

#define BYTECLK_MUX_1_CLK	28

#define PCLK_SRC_MUX_1_CLK	29

#define PCLK_SRC_1_CLK		30

#define PCLK_MUX_1_CLK		31

/* CPHY clocks for DSI-1 PLL */

#define CPHY_BYTECLK_SRC_1_CLK	32

#define POST_VCO_DIV3_5_1_CLK	33

#define CPHY_PCLK_SRC_MUX_1_CLK	34

#define CPHY_PCLK_SRC_1_CLK	35



#define SHADOW_VCO_CLK_1		36

#define SHADOW_PLL_OUT_DIV_1_CLK	37

#define SHADOW_BITCLK_SRC_1_CLK		38

#define SHADOW_BYTECLK_SRC_1_CLK	39

#define SHADOW_POST_BIT_DIV_1_CLK	40

#define SHADOW_POST_VCO_DIV_1_CLK	41

#define SHADOW_PCLK_SRC_MUX_1_CLK	42

#define SHADOW_PCLK_SRC_1_CLK		43



/* DP PLL clocks */

#define	DP_VCO_CLK	0