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Commit 06c02c12 authored by Runmin Wang's avatar Runmin Wang
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ARM: dts: msm: Add L1 cache definitions to sdm855 



Add initial L1 I/D cache nodes to sdm855 DT node.

Change-Id: I68ef91513bf581b7ede75becea74ffe8957e7682
Signed-off-by: default avatarRunmin Wang <runminw@codeaurora.org>
parent c9395a83
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