Merge "msm: ep_pcie: Update L1 programming sequence" (06518ce3) · Commits · e / devices / android_kernel_xiaomi_sm6125

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+5 −8

Original line number	Diff line number	Diff line
		@@ -625,15 +625,16 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
		ep_pcie_write_mask(dev->dm_core +
		PCIE20_LINK_CONTROL2_LINK_STATUS2,
		0xf, dev->link_speed);

		EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n",
		dev->rev);
		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
		}

		if (dev->active_config) {
		struct resource *dbi = dev->res[EP_PCIE_RES_DM_CORE].resource;
		u32 dbi_lo = dbi->start;

		EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1\n", dev->rev);
		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);

		ep_pcie_write_reg(dev->parf + PCIE20_PARF_SLV_ADDR_MSB_CTRL,
		0, BIT(0));
		ep_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI,
		@@ -820,13 +821,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
		readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));
		}

		if (dev->active_config) {
		if (dev->active_config)
		ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14);

		EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1\n", dev->rev);
		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
		}

		if (!configured)
		ep_pcie_config_mmio(dev);
		}