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Commit 2ce7a4ff authored by Siddartha Mohanadoss's avatar Siddartha Mohanadoss Committed by Gerrit - the friendly Code Review server
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msm: ep_pcie: Update L1 programming sequence 



L1 requires updated PHY which is programmed by the
HLOS driver after one cycle of D3_COLD followed by D0 entry.
The PHY sequence from PBL does not support L1 therefore
disable L1 until the new PHY sequence gets programmed.

Change-Id: I041b3e7db86d6985400ce6d218b7a363f915d9cf
Signed-off-by: default avatarSiddartha Mohanadoss <smohanad@codeaurora.org>
parent 67cf5d7d

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+5 −8
Original line number Diff line number Diff line
@@ -625,15 +625,16 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
		ep_pcie_write_mask(dev->dm_core +

				PCIE20_LINK_CONTROL2_LINK_STATUS2,

				0xf, dev->link_speed);



		EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n",

				dev->rev);

		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);

	}



	if (dev->active_config) {

		struct resource *dbi = dev->res[EP_PCIE_RES_DM_CORE].resource;

		u32 dbi_lo = dbi->start;



		EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1\n", dev->rev);

		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);



		ep_pcie_write_reg(dev->parf + PCIE20_PARF_SLV_ADDR_MSB_CTRL,

					0, BIT(0));

		ep_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI,
@@ -820,13 +821,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
			readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));

	}



	if (dev->active_config) {

	if (dev->active_config)

		ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14);



		EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1\n", dev->rev);

		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);

	}



	if (!configured)

		ep_pcie_config_mmio(dev);

}