clk: qcom: gcc-sm8150: Update the halt_check flag for the PCIe pipe clocks

The gcc_pcie_0_pipe_clk and gcc_pcie_1_pipe_clk clocks are sourced off
of the PCIe PHY. There's a circular dependency between the PHY and its
corresponding pipe clock where the pipe clock does not turn on until
the PHY is up but the PHY itself relies on a feedback signal from the
pipe clock for it to turn on. This results in a long delay whilst
enabling the pipe clocks, greater than 1 msec in some instances.
Since it's not advisable for the clock driver to hold on to a spinlock
whilst disabling interrupts for so long, move the status check to the
PCIe client driver instead.

Change-Id: I9da4bcf9b20dc1c5c763cd6331b55ae5437c9efb
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>