Loading arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi +2 −0 Original line number Original line Diff line number Diff line Loading @@ -98,6 +98,8 @@ /* GDSC oxili regulators */ /* GDSC oxili regulators */ vddcx-supply = <&gpu_cx_gdsc>; vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; /* Cx ipeak limit supprt */ qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>; /* CPU latency parameter */ /* CPU latency parameter */ qcom,pm-qos-active-latency = <67>; qcom,pm-qos-active-latency = <67>; Loading arch/arm64/boot/dts/qcom/sm6150.dtsi +5 −0 Original line number Original line Diff line number Diff line Loading @@ -2849,6 +2849,11 @@ qcom,msm-bus,active-only; qcom,msm-bus,active-only; status = "ok"; status = "ok"; }; }; cx_ipeak_lm: cx_ipeak@01fed000 { compatible = "qcom,cx-ipeak-sm6150"; reg = <0x1fed000 0x28>; }; }; }; #include "pm6150.dtsi" #include "pm6150.dtsi" Loading Loading
arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi +2 −0 Original line number Original line Diff line number Diff line Loading @@ -98,6 +98,8 @@ /* GDSC oxili regulators */ /* GDSC oxili regulators */ vddcx-supply = <&gpu_cx_gdsc>; vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; /* Cx ipeak limit supprt */ qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>; /* CPU latency parameter */ /* CPU latency parameter */ qcom,pm-qos-active-latency = <67>; qcom,pm-qos-active-latency = <67>; Loading
arch/arm64/boot/dts/qcom/sm6150.dtsi +5 −0 Original line number Original line Diff line number Diff line Loading @@ -2849,6 +2849,11 @@ qcom,msm-bus,active-only; qcom,msm-bus,active-only; status = "ok"; status = "ok"; }; }; cx_ipeak_lm: cx_ipeak@01fed000 { compatible = "qcom,cx-ipeak-sm6150"; reg = <0x1fed000 0x28>; }; }; }; #include "pm6150.dtsi" #include "pm6150.dtsi" Loading