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Commit fa18d318 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add sleep clock for HS PHY on QCS405"

parents 48d09ab1 b4deace9

arch/arm64/boot/dts/qcom/qcs405-usb.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -79,8 +79,9 @@ 
		qcom,vdd-voltage-level = <0 1144000 1200000>;



		clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>,

			 <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>;

		clock-names = "ref_clk", "phy_csr_clk";

			 <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,

			 <&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>;

		clock-names = "ref_clk", "phy_csr_clk", "sleep_clk";



		resets = <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,

			 <&clock_gcc GCC_USB2A_PHY_BCR>;
@@ -184,8 +185,9 @@ 
		qcom,vdd-voltage-level = <0 1144000 1200000>;



		clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>,

			 <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>;

		clock-names = "ref_clk", "phy_csr_clk";

			 <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,

			 <&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>;

		clock-names = "ref_clk", "phy_csr_clk", "sleep_clk";



		resets = <&clock_gcc GCC_QUSB2_PHY_BCR>,

			 <&clock_gcc GCC_USB2_HS_PHY_ONLY_BCR>;