arm64: tlbflush: avoid writing RES0 bits

Several of the bits of the TLBI register operand are RES0 per the ARM
ARM, so TLBI operations should avoid writing non-zero values to these
bits.

This patch adds a macro __TLBI_VADDR(addr, asid) that creates the
operand register in the correct format and honors the RES0 bits.

Change-Id: I793b7c9fb537f19a840a1644ed761524cd540687
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Philip Elcan <pelcan@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-Commit: 7f170499f734c417290518aa50cac11953bf8161
Git-Repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>