ARM: dts: msm: Add PHY clocks for SS PHY on QCS405

Add the gcc pipe clock handle to enable pipe clock
from SS PHY to core and the cfg_ahb_clk to access
the CSR registers to configure SS PHY.
Also correct the CSR register base address for SS PHY.

Change-Id: Idbc20899c8cbbecc2f8e0d13246a66a66356bf08
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>