Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e82ba578 authored by Pankaj Dubey's avatar Pankaj Dubey Committed by Tomasz Figa
Browse files

clk: samsung: exynos3250: fix width field of mout_mmc0/1 



As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.

Signed-off-by: default avatarPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: default avatarTomasz Figa <tomasz.figa@gmail.com>
parent 59037b92

drivers/clk/samsung/clk-exynos3250.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -354,8 +354,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = { 




	/* SRC_FSYS */

	/* SRC_FSYS */

	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),

	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),

	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),

	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),

	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),

	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),





	/* SRC_PERIL0 */

	/* SRC_PERIL0 */

	MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),

	MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),