Loading Documentation/admin-guide/kernel-parameters.txt +9 −7 Original line number Original line Diff line number Diff line Loading @@ -2402,8 +2402,8 @@ http://repo.or.cz/w/linux-2.6/mini2440.git http://repo.or.cz/w/linux-2.6/mini2440.git mitigations= mitigations= [X86,PPC,S390] Control optional mitigations for CPU [X86,PPC,S390,ARM64] Control optional mitigations for vulnerabilities. This is a set of curated, CPU vulnerabilities. This is a set of curated, arch-independent options, each of which is an arch-independent options, each of which is an aggregation of existing arch-specific options. aggregation of existing arch-specific options. Loading @@ -2412,12 +2412,14 @@ improves system performance, but it may also improves system performance, but it may also expose users to several CPU vulnerabilities. expose users to several CPU vulnerabilities. Equivalent to: nopti [X86,PPC] Equivalent to: nopti [X86,PPC] kpti=0 [ARM64] nospectre_v1 [PPC] nospectre_v1 [PPC] nobp=0 [S390] nobp=0 [S390] nospectre_v1 [X86] nospectre_v1 [X86] nospectre_v2 [X86,PPC,S390] nospectre_v2 [X86,PPC,S390,ARM64] spectre_v2_user=off [X86] spectre_v2_user=off [X86] spec_store_bypass_disable=off [X86,PPC] spec_store_bypass_disable=off [X86,PPC] ssbd=force-off [ARM64] l1tf=off [X86] l1tf=off [X86] mds=off [X86] mds=off [X86] Loading Loading @@ -2758,10 +2760,10 @@ (bounds check bypass). With this option data leaks (bounds check bypass). With this option data leaks are possible in the system. are possible in the system. nospectre_v2 [X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for (indirect branch prediction) vulnerability. System may the Spectre variant 2 (indirect branch prediction) allow data leaks with this option, which is equivalent vulnerability. System may allow data leaks with this to spectre_v2=off. option. nospec_store_bypass_disable nospec_store_bypass_disable [HW] Disable all mitigations for the Speculative Store Bypass vulnerability [HW] Disable all mitigations for the Speculative Store Bypass vulnerability Loading Documentation/arm64/cpu-feature-registers.txt +14 −3 Original line number Original line Diff line number Diff line Loading @@ -111,6 +111,9 @@ infrastructure: | Name | bits | visible | | Name | bits | visible | |--------------------------------------------------| |--------------------------------------------------| | RES0 | [63-48] | n | | RES0 | [63-48] | n | | TS | [55-52] | y | |--------------------------------------------------| | FHM | [51-48] | y | |--------------------------------------------------| |--------------------------------------------------| | DP | [47-44] | y | | DP | [47-44] | y | |--------------------------------------------------| |--------------------------------------------------| Loading @@ -133,8 +136,6 @@ infrastructure: | SHA1 | [11-8] | y | | SHA1 | [11-8] | y | |--------------------------------------------------| |--------------------------------------------------| | AES | [7-4] | y | | AES | [7-4] | y | |--------------------------------------------------| | RES0 | [3-0] | n | x--------------------------------------------------x x--------------------------------------------------x Loading @@ -142,7 +143,9 @@ infrastructure: x--------------------------------------------------x x--------------------------------------------------x | Name | bits | visible | | Name | bits | visible | |--------------------------------------------------| |--------------------------------------------------| | RES0 | [63-28] | n | | DIT | [51-48] | y | |--------------------------------------------------| | SVE | [35-32] | y | |--------------------------------------------------| |--------------------------------------------------| | GIC | [27-24] | n | | GIC | [27-24] | n | |--------------------------------------------------| |--------------------------------------------------| Loading Loading @@ -193,6 +196,14 @@ infrastructure: | DPB | [3-0] | y | | DPB | [3-0] | y | x--------------------------------------------------x x--------------------------------------------------x 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| | AT | [35-32] | y | x--------------------------------------------------x Appendix I: Example Appendix I: Example --------------------------- --------------------------- Loading Makefile +1 −1 Original line number Original line Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0 VERSION = 4 VERSION = 4 PATCHLEVEL = 14 PATCHLEVEL = 14 SUBLEVEL = 150 SUBLEVEL = 151 EXTRAVERSION = EXTRAVERSION = NAME = Petit Gorille NAME = Petit Gorille Loading arch/arm/boot/dts/am4372.dtsi +2 −0 Original line number Original line Diff line number Diff line Loading @@ -1118,6 +1118,8 @@ ti,hwmods = "dss_dispc"; ti,hwmods = "dss_dispc"; clocks = <&disp_clk>; clocks = <&disp_clk>; clock-names = "fck"; clock-names = "fck"; max-memory-bandwidth = <230000000>; }; }; rfbi: rfbi@4832a800 { rfbi: rfbi@4832a800 { Loading arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +2 −1 Original line number Original line Diff line number Diff line Loading @@ -966,7 +966,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { .rev_offs = 0x0000, .rev_offs = 0x0000, .sysc_offs = 0x0010, .sysc_offs = 0x0010, .syss_offs = 0x0014, .syss_offs = 0x0014, .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS, .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP), SIDLE_SMART_WKUP), .sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2, Loading Loading
Documentation/admin-guide/kernel-parameters.txt +9 −7 Original line number Original line Diff line number Diff line Loading @@ -2402,8 +2402,8 @@ http://repo.or.cz/w/linux-2.6/mini2440.git http://repo.or.cz/w/linux-2.6/mini2440.git mitigations= mitigations= [X86,PPC,S390] Control optional mitigations for CPU [X86,PPC,S390,ARM64] Control optional mitigations for vulnerabilities. This is a set of curated, CPU vulnerabilities. This is a set of curated, arch-independent options, each of which is an arch-independent options, each of which is an aggregation of existing arch-specific options. aggregation of existing arch-specific options. Loading @@ -2412,12 +2412,14 @@ improves system performance, but it may also improves system performance, but it may also expose users to several CPU vulnerabilities. expose users to several CPU vulnerabilities. Equivalent to: nopti [X86,PPC] Equivalent to: nopti [X86,PPC] kpti=0 [ARM64] nospectre_v1 [PPC] nospectre_v1 [PPC] nobp=0 [S390] nobp=0 [S390] nospectre_v1 [X86] nospectre_v1 [X86] nospectre_v2 [X86,PPC,S390] nospectre_v2 [X86,PPC,S390,ARM64] spectre_v2_user=off [X86] spectre_v2_user=off [X86] spec_store_bypass_disable=off [X86,PPC] spec_store_bypass_disable=off [X86,PPC] ssbd=force-off [ARM64] l1tf=off [X86] l1tf=off [X86] mds=off [X86] mds=off [X86] Loading Loading @@ -2758,10 +2760,10 @@ (bounds check bypass). With this option data leaks (bounds check bypass). With this option data leaks are possible in the system. are possible in the system. nospectre_v2 [X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for (indirect branch prediction) vulnerability. System may the Spectre variant 2 (indirect branch prediction) allow data leaks with this option, which is equivalent vulnerability. System may allow data leaks with this to spectre_v2=off. option. nospec_store_bypass_disable nospec_store_bypass_disable [HW] Disable all mitigations for the Speculative Store Bypass vulnerability [HW] Disable all mitigations for the Speculative Store Bypass vulnerability Loading
Documentation/arm64/cpu-feature-registers.txt +14 −3 Original line number Original line Diff line number Diff line Loading @@ -111,6 +111,9 @@ infrastructure: | Name | bits | visible | | Name | bits | visible | |--------------------------------------------------| |--------------------------------------------------| | RES0 | [63-48] | n | | RES0 | [63-48] | n | | TS | [55-52] | y | |--------------------------------------------------| | FHM | [51-48] | y | |--------------------------------------------------| |--------------------------------------------------| | DP | [47-44] | y | | DP | [47-44] | y | |--------------------------------------------------| |--------------------------------------------------| Loading @@ -133,8 +136,6 @@ infrastructure: | SHA1 | [11-8] | y | | SHA1 | [11-8] | y | |--------------------------------------------------| |--------------------------------------------------| | AES | [7-4] | y | | AES | [7-4] | y | |--------------------------------------------------| | RES0 | [3-0] | n | x--------------------------------------------------x x--------------------------------------------------x Loading @@ -142,7 +143,9 @@ infrastructure: x--------------------------------------------------x x--------------------------------------------------x | Name | bits | visible | | Name | bits | visible | |--------------------------------------------------| |--------------------------------------------------| | RES0 | [63-28] | n | | DIT | [51-48] | y | |--------------------------------------------------| | SVE | [35-32] | y | |--------------------------------------------------| |--------------------------------------------------| | GIC | [27-24] | n | | GIC | [27-24] | n | |--------------------------------------------------| |--------------------------------------------------| Loading Loading @@ -193,6 +196,14 @@ infrastructure: | DPB | [3-0] | y | | DPB | [3-0] | y | x--------------------------------------------------x x--------------------------------------------------x 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| | AT | [35-32] | y | x--------------------------------------------------x Appendix I: Example Appendix I: Example --------------------------- --------------------------- Loading
Makefile +1 −1 Original line number Original line Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0 VERSION = 4 VERSION = 4 PATCHLEVEL = 14 PATCHLEVEL = 14 SUBLEVEL = 150 SUBLEVEL = 151 EXTRAVERSION = EXTRAVERSION = NAME = Petit Gorille NAME = Petit Gorille Loading
arch/arm/boot/dts/am4372.dtsi +2 −0 Original line number Original line Diff line number Diff line Loading @@ -1118,6 +1118,8 @@ ti,hwmods = "dss_dispc"; ti,hwmods = "dss_dispc"; clocks = <&disp_clk>; clocks = <&disp_clk>; clock-names = "fck"; clock-names = "fck"; max-memory-bandwidth = <230000000>; }; }; rfbi: rfbi@4832a800 { rfbi: rfbi@4832a800 { Loading
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +2 −1 Original line number Original line Diff line number Diff line Loading @@ -966,7 +966,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { .rev_offs = 0x0000, .rev_offs = 0x0000, .sysc_offs = 0x0010, .sysc_offs = 0x0010, .syss_offs = 0x0014, .syss_offs = 0x0014, .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS, .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP), SIDLE_SMART_WKUP), .sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2, Loading
