arm64: Add workaround for Cortex-A76 erratum 1286807

On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual address
for a cacheable mapping of a location is being accessed by a core while
another core is remapping the virtual address to a new physical page
using the recommended break-before-make sequence, then under very rare
circumstances TLBI+DSB completes before a read using the translation
being invalidated has been observed by other observers. The workaround
repeats the TLBI+DSB operation and is shared with the Qualcomm Falkor
erratum 1009.

Change-Id: I6bbc17351994c7474e14c9dfcbe3b4b2c5d3f2c8
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Git-Commit: ce8c80c536dac9f325a051b30bf7730ee505eddc
Git-Repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


[sudaraja@codeaurora.org: added Cortex-A76 MIDR type, used existing midr range defines]
Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>