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Commit dcd6f513 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: ipa4: Update IPA_CFG registers for IPA4.5"

parents fa18d318 7baca9fb

drivers/platform/msm/ipa/ipa_v3/ipa.c

+8 −7
Original line number Diff line number Diff line
@@ -4511,6 +4511,7 @@ static int ipa3_post_init(const struct ipa3_plat_drv_res *resource_p, 
	IPADBG("IPA HW initialization sequence completed");



	ipa3_ctx->ipa_num_pipes = ipa3_get_num_pipes();

	IPADBG("IPA Pipes num %u\n", ipa3_ctx->ipa_num_pipes);

	if (ipa3_ctx->ipa_num_pipes > IPA3_MAX_NUM_PIPES) {

		IPAERR("IPA has more pipes then supported has %d, max %d\n",

			ipa3_ctx->ipa_num_pipes, IPA3_MAX_NUM_PIPES);
@@ -5136,13 +5137,13 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, 
			ipa3_ctx->ipa_tz_unlock_reg[i].size =

				resource_p->ipa_tz_unlock_reg[i].size;

		}

	}



		/* unlock registers for uc */

		result = ipa3_tz_unlock_reg(ipa3_ctx->ipa_tz_unlock_reg,

					    ipa3_ctx->ipa_tz_unlock_reg_num);

		if (result)

			IPAERR("Failed to unlock memory region using TZ\n");

	}



	/* default aggregation parameters */

	ipa3_ctx->aggregation_type = IPA_MBIM_16;
@@ -5744,7 +5745,7 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, 
	ipa_drv_res->use_ipa_teth_bridge =

			of_property_read_bool(pdev->dev.of_node,

			"qcom,use-ipa-tethering-bridge");

	IPADBG(": using TBDr = %s",

	IPADBG(": using ipa teth bridge = %s",

		ipa_drv_res->use_ipa_teth_bridge

		? "True" : "False");

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+43 −50
Original line number Diff line number Diff line
@@ -2977,7 +2977,7 @@ int ipa3_resume_resource(enum ipa_rm_resource_name resource) 
 *

 * Return value: HW type index

 */

u8 ipa3_get_hw_type_index(void)

static u8 ipa3_get_hw_type_index(void)

{

	u8 hw_type_index;
@@ -3221,6 +3221,7 @@ int ipa3_init_hw(void) 


	/* Read IPA version and make sure we have access to the registers */

	ipa_version = ipahal_read_reg(IPA_VERSION);

	IPADBG("IPA_VERSION=%u\n", ipa_version);

	if (ipa_version == 0)

		return -EFAULT;
@@ -3246,7 +3247,8 @@ int ipa3_init_hw(void) 
		break;

	}



	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) {

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 &&

		ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) {

		struct ipahal_reg_clkon_cfg clkon_cfg;

		struct ipahal_reg_tx_cfg tx_cfg;
@@ -6124,6 +6126,38 @@ static void ipa3_configure_rx_hps_weight(void) 
	ipahal_write_reg_fields(IPA_HPS_FTCH_ARB_QUEUE_WEIGHT, &val);

}



static void ipa3_configure_rx_hps(void)

{

	int rx_hps_max_clnt_in_depth0;



	IPADBG("Assign RX_HPS CMDQ rsrc groups min-max limits\n");



	/* Starting IPA4.5 we have 5 RX_HPS_CMDQ */

	if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5)

		rx_hps_max_clnt_in_depth0 = 4;

	else

		rx_hps_max_clnt_in_depth0 = 5;



	ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, true);

	ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, false);



	/*

	 * IPA 3.0/3.1 uses 6 RX_HPS_CMDQ and needs depths1 for that

	 * which has two clients

	 */

	if (ipa3_ctx->ipa_hw_type <= IPA_HW_v3_1) {

		ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0,

			true);

		ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0,

			false);

	}



	/* Starting IPA4.2 no support to HPS weight config */

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5 &&

		(ipa3_ctx->ipa_hw_type < IPA_HW_v4_2))

		ipa3_configure_rx_hps_weight();

}



void ipa3_set_resorce_groups_min_max_limits(void)

{

	int i;
@@ -6134,7 +6168,6 @@ void ipa3_set_resorce_groups_min_max_limits(void) 
	int dst_grp_idx_max;

	struct ipahal_reg_rsrc_grp_cfg val;

	u8 hw_type_idx;

	int rx_hps_max_clnt_in_depth0;



	IPADBG("ENTER\n");
@@ -6211,40 +6244,15 @@ void ipa3_set_resorce_groups_min_max_limits(void) 
		}

	}



	/* move rx_hps resource group configuration from HLOS to TZ */

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1 &&

	    ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION) {

		IPAERR("skip configuring ipa_rx_hps_clients from HLOS\n");

		return;

	}



	IPADBG("Assign RX_HPS CMDQ rsrc groups min-max limits\n");



	/* Starting IPA4.5 have 5 RX_HPS_CMDQ */

	if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5)

		rx_hps_max_clnt_in_depth0 = 4;

	else

		rx_hps_max_clnt_in_depth0 = 5;



	ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, true);

	ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, false);



	/*

	 * IPA 3.0/3.1 uses 6 RX_HPS_CMDQ and needs depths1 for that

	 * which has two clients

	/* move rx_hps resource group configuration from HLOS to TZ

	 * on real platform with IPA 3.1 or later

	 */

	if (ipa3_ctx->ipa_hw_type <= IPA_HW_v3_1) {

		ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0,

			true);

		ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0,

			false);

	if (ipa3_ctx->ipa_hw_type < IPA_HW_v3_1 ||

		ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL ||

		ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) {

		ipa3_configure_rx_hps();

	}



	/* Starting IPA4.2 no support to HPS weight config */

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5 &&

		(ipa3_ctx->ipa_hw_type < IPA_HW_v4_2))

		ipa3_configure_rx_hps_weight();



	IPADBG("EXIT\n");

}
@@ -6723,10 +6731,9 @@ int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base, 


/*

 * The following needed for the EMULATION system. On a non-emulation

 * system (ie. the real UE), this is functionality is done in the

 * system (ie. the real UE), this functionality is done in the

 * TZ...

 */

#define IPA_SPARE_REG_1_VAL (0xC0000805)



static void ipa_gsi_setup_reg(void)

{
@@ -6740,13 +6747,6 @@ static void ipa_gsi_setup_reg(void) 
	/* enable GSI interface */

	ipahal_write_reg(IPA_GSI_CONF, 1);



	/*

	 * Before configuring the FIFOs need to unset bit 30 in the

	 * spare register

	 */

	ipahal_write_reg(IPA_SPARE_REG_1,

			 (IPA_SPARE_REG_1_VAL & (~(1 << 30))));



	/* setup IPA_ENDP_GSI_CFG_TLV_n reg */

	start = 0;

	ipa3_ctx->ipa_num_pipes = ipa3_get_num_pipes();
@@ -6802,13 +6802,6 @@ static void ipa_gsi_setup_reg(void) 
		reg_val = 0;

		ipahal_write_reg_n(IPA_ENDP_GSI_CFG2_n, i, reg_val);

	}



	/*

	 * After configuring the FIFOs need to set bit 30 in the spare

	 * register

	 */

	ipahal_write_reg(IPA_SPARE_REG_1,

			 (IPA_SPARE_REG_1_VAL | (1 << 30)));

}



/**

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+388 −117

File changed.

Preview size limit exceeded, changes collapsed.

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

+24 −13
Original line number Diff line number Diff line
@@ -34,17 +34,16 @@ enum ipahal_reg_name { 
	IPA_HOLB_DROP_IRQ_CLR_EE_n,

	IPA_BCR,

	IPA_ENABLED_PIPES,

	IPA_COMP_SW_RESET,

	IPA_VERSION,

	IPA_TAG_TIMER,

	IPA_COMP_HW_VERSION,

	IPA_SPARE_REG_1,

	IPA_SPARE_REG_2,

	IPA_COMP_CFG,

	IPA_STATE_TX_WRAPPER,

	IPA_STATE_TX1,

	IPA_STATE_FETCHER,

	IPA_STATE_FETCHER_MASK,

	IPA_STATE_FETCHER_MASK_0,

	IPA_STATE_FETCHER_MASK_1,

	IPA_STATE_DFETCHER,

	IPA_STATE_ACL,

	IPA_STATE,
@@ -56,6 +55,12 @@ enum ipahal_reg_name { 
	IPA_STATE_GSI_AOS,

	IPA_STATE_GSI_IF,

	IPA_STATE_GSI_SKIP,

	IPA_STATE_GSI_IF_CONS,

	IPA_STATE_DPL_FIFO,

	IPA_STATE_COAL_MASTER,

	IPA_GENERIC_RAM_ARBITER_PRIORITY,

	IPA_STATE_NLO_AGGR,

	IPA_STATE_COAL_MASTER_1,

	IPA_ENDP_INIT_HDR_n,

	IPA_ENDP_INIT_HDR_EXT_n,

	IPA_ENDP_INIT_AGGR_n,
@@ -88,8 +93,7 @@ enum ipahal_reg_name { 
	IPA_SYS_PKT_PROC_CNTXT_BASE,

	IPA_LOCAL_PKT_PROC_CNTXT_BASE,

	IPA_ENDP_STATUS_n,

	IPA_ENDP_WEIGHTS_n,

	IPA_ENDP_YELLOW_RED_MARKER,

	IPA_ENDP_YELLOW_RED_MARKER_CFG_n,

	IPA_ENDP_FILTER_ROUTER_HSH_CFG_n,

	IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n,

	IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n,
@@ -221,7 +225,7 @@ struct ipahal_reg_shared_mem_size { 
 *	If set to 0 (default), PKT-STATUS will be appended before the packet

 *	for this endpoint. If set to 1, PKT-STATUS will be appended after the

 *	packet for this endpoint. Valid only for Output Pipes (IPA Producer)

 * @status_pkt_suppress:

 * @status_pkt_suppress: Disable notification status, when statistics is enabled

 */

struct ipahal_reg_ep_cfg_status {

	bool status_en;
@@ -239,6 +243,7 @@ struct ipahal_reg_ep_cfg_status { 
 *	to IPA_RX sub-module and open_global refers to global IPA 1x clock

 */

struct ipahal_reg_clkon_cfg {

	bool open_dpl_fifo;

	bool open_global_2x_clk;

	bool open_global;

	bool open_gsi_if;
@@ -274,12 +279,12 @@ struct ipahal_reg_clkon_cfg { 
/*

 * struct ipahal_reg_comp_cfg- IPA Core QMB/Master Port selection

 *

 * @all: QMB/Master port selection policy is configured via IPA_COMP_CFG

 *	- Address based Selection

 *	- Endpoint based selection / Legacy Mode

 * @enable / @ipa_dcmp_fast_clk_en: are not relevant starting IPA4.5

 * @ipa_full_flush_wait_rsc_closure_en: relevant starting IPA4.5

 */

struct ipahal_reg_comp_cfg {

	bool ipa_atomic_fetcher_arb_lock_dis;

	bool ipa_full_flush_wait_rsc_closure_en;

	u8 ipa_atomic_fetcher_arb_lock_dis;

	bool ipa_qmb_select_by_address_global_en;

	bool gsi_multi_axi_masters_dis;

	bool gsi_snoc_cnoc_loop_protection_disable;
@@ -504,10 +509,12 @@ struct ipahal_reg_qsb_max_reads { 
 * @tx1_prefetch_disable: Disable prefetch on TX1

 * @tx0_prefetch_almost_empty_size: Prefetch almost empty size on TX0

 * @tx1_prefetch_almost_empty_size: Prefetch almost empty size on TX1

 * @dmaw_scnd_outsd_pred_threshold:

 * @dmaw_scnd_outsd_pred_threshold: threshold for DMAW_SCND_OUTSD_PRED_EN

 * @dmaw_max_beats_256_dis:

 * @dmaw_scnd_outsd_pred_en:

 * @pa_mask_en:

 * @dual_tx_enable: When 1 TX0 and TX1 are enabled. When 0 only TX0 is enabled

 *  Relevant starting IPA4.5

 */

struct ipahal_reg_tx_cfg {

	bool tx0_prefetch_disable;
@@ -518,7 +525,7 @@ struct ipahal_reg_tx_cfg { 
	u32 dmaw_max_beats_256_dis;

	u32 dmaw_scnd_outsd_pred_en;

	u32 pa_mask_en;



	bool dual_tx_enable;

};



/*
@@ -539,7 +546,11 @@ struct ipahal_ep_cfg_ctrl_scnd { 
	bool endp_delay;

};





/*

 * ipahal_print_all_regs() - Loop and read and print all the valid registers

 *  Parameterized registers are also printed for all the valid ranges.

 *  Print to dmsg and IPC logs

 */

void ipahal_print_all_regs(bool print_to_dmesg);



/*

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h

+59 −1
Original line number Diff line number Diff line
@@ -95,6 +95,10 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V3_5 0

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_0 0x7fffff

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_0 0

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_2 0x1ffff

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_2 0

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_5 0x7fffffff

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_5 0



/* IPA_ENDP_INIT_ROUTE_n register */

#define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK 0x1f
@@ -114,6 +118,19 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x7

#define IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0



#define IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK_V4_5 0x20000000

#define IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT_V4_5 0x1d

#define IPA_ENDP_INIT_MODE_n_PIPE_REPLICATION_EN_BMSK_V4_5 0x10000000

#define IPA_ENDP_INIT_MODE_n_PIPE_REPLICATION_EN_SHFT_V4_5 0x1c

#define IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK_V4_5 0xffff000

#define IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT_V4_5 0xc

#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V4_5 0x1f0

#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V4_5 0x4

#define IPA_ENDP_INIT_MODE_n_DCPH_ENABLE_BMSK_V4_5 0x8

#define IPA_ENDP_INIT_MODE_n_DCPH_ENABLE_SHFT_V4_5 0x3

#define IPA_ENDP_INIT_MODE_n_MODE_BMSK_V4_5 0x7

#define IPA_ENDP_INIT_MODE_n_MODE_SHFT_V4_5 0x0



/* IPA_ENDP_INIT_NAT_n register */

#define IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3

#define IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0
@@ -197,6 +214,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v3_5 0x3

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v3_5 0

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_5 0x7

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_5 0



/* IPA_SHARED_MEM_SIZE register */

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000
@@ -252,6 +271,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0



/* IPA_CLKON_CFG register */

#define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_BMSK_V4_5  0x40000000

#define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_SHFT_V4_5 30

#define IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_BMSK  0x20000000

#define IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_SHFT 29

#define IPA_CLKON_CFG_OPEN_GLOBAL_BMSK 0x10000000
@@ -407,7 +428,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5 (0x1C)

#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5 (2)



/* IPA_TX_CFG register v4.0 */

#define IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5 (0x20000)

#define IPA_TX_CFG_DUAL_TX_ENABLE_SHFT_V4_5 (0x11)

#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0 (0x1e000)

#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT_V4_0 (0xd)

#define IPA_TX_CFG_PA_MASK_EN_BMSK_V4_0 (0x1000)
@@ -479,4 +501,40 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_COMP_CFG_ENABLE_BMSK 0x1

#define IPA_COMP_CFG_ENABLE_SHFT 0



#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_5 0x200000

#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_5 21

#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_5 0x1E0000

#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_5 17

#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK_v4_5 0x10000

#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT_v4_5 16

#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK_v4_5 0x8000

#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT_v4_5 15

#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK_v4_5 0x4000

#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT_v4_5 14

#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK_v4_5 \

									0x2000

#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT_v4_5 13

#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK_v4_5 0x1000

#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT_v4_5 12

#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK_v4_5 0x800

#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT_v4_5 11

#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK_v4_5 0x400

#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT_v4_5 10

#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK_v4_5 0x200

#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT_v4_5 9

#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK_v4_5 0x100

#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT_v4_5 8

#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK_v4_5 0x80

#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT_v4_5 7

#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK_v4_5 0x40

#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT_v4_5 6

#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK_v4_5 0x20

#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT_v4_5 5

#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK_v4_5 0x8

#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT_v4_5 3

#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK_v4_5 0x4

#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT_v4_5 2

#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK_v4_5 0x2

#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT_v4_5 1



#endif /* _IPAHAL_REG_I_H_ */