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Unverified Commit d5cc0a1f authored Jan 02, 2018 by Pardha Saradhi K Committed by Mark Brown Jan 03, 2018

ASoC: Intel: Skylake: Disable clock gating during firmware and library download



During firmware and library download, sometimes it is observed that
firmware and library download is timed-out resulting into probe failure.

This patch disables dynamic clock gating while firmware and library
download.

Signed-off-by: Pardha Saradhi K <pardha.saradhi.kesapragada@intel.com>
Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com>
Signed-off-by: Guneshwor Singh <guneshwor.o.singh@intel.com>
Acked-By: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

parent 752c93aa

sound/soc/intel/skylake/skl-messages.c

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -417,7 +417,11 @@ int skl_resume_dsp(struct skl *skl)
	if (skl->skl_sst->is_first_boot == true)		if (skl->skl_sst->is_first_boot == true)
	return 0;		return 0;

			/* disable dynamic clock gating during fw and lib download */
			ctx->enable_miscbdcge(ctx->dev, false);

	ret = skl_dsp_wake(ctx->dsp);		ret = skl_dsp_wake(ctx->dsp);
			ctx->enable_miscbdcge(ctx->dev, true);
	if (ret < 0)		if (ret < 0)
	return ret;		return ret;

sound/soc/intel/skylake/skl-pcm.c

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1342,7 +1342,11 @@ static int skl_platform_soc_probe(struct snd_soc_platform *platform)
	return -EIO;		return -EIO;
	}		}

			/* disable dynamic clock gating during fw and lib download */
			skl->skl_sst->enable_miscbdcge(platform->dev, false);

	ret = ops->init_fw(platform->dev, skl->skl_sst);		ret = ops->init_fw(platform->dev, skl->skl_sst);
			skl->skl_sst->enable_miscbdcge(platform->dev, true);
	if (ret < 0) {		if (ret < 0) {
	dev_err(platform->dev, "Failed to boot first fw: %d\n", ret);		dev_err(platform->dev, "Failed to boot first fw: %d\n", ret);
	return ret;		return ret;