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Commit d5154373 authored by Da Hoon Pyun's avatar Da Hoon Pyun Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Enable npudsp_npu_ddr_bw for atoll 



This change is to enable npudsp ddr bw for the atoll platform.

Change-Id: I3a53abba79b06f87373204bad07258916a6aaf94
Signed-off-by: default avatarDa Hoon Pyun <dpyun@codeaurora.org>
parent 2b35f93b

arch/arm64/boot/dts/qcom/atoll-npu.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -65,8 +65,8 @@ 
			<&apcs_glb2 6>;

		mbox-names = "glink", "smp2p";

		#mbox-cells = <1>;

		qcom,npubw-devs = <&npu_npu_ddr_bw>;

		qcom,npubw-dev-names = "ddr_bw";

		qcom,npubw-devs = <&npu_npu_ddr_bw>, <&npudsp_npu_ddr_bw>;

		qcom,npubw-dev-names = "ddr_bw", "dsp_ddr_bw";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		qcom,npu-pwrlevels {

			#address-cells = <1>;

arch/arm64/boot/dts/qcom/atoll.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -3383,7 +3383,7 @@ 
		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		status = "disabled";

		status = "ok";

	};



	npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70300 {
@@ -3401,7 +3401,7 @@ 
		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npudsp_npu_ddr_bw>;

		qcom,count-unit = <0x10000>;

		status = "disabled";

		status = "ok";

	};



	keepalive_opp_table: keepalive-opp-table {