drivers: clk: qcom: enable clk enable select bit during FIFO resync

For each clock state change on DSI link clocks, toggling
of resync fifo register is needed. During this operation
clk_en_sel bit should be set high per hardware
recommendations.

Change-Id: Ie1ee73d36d5add929a72796c465d3850c1d61f2a
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>