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Commit cd4e1939 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

clk: qcom: Update ops for PLLs which support slewing 



When enabling the PLL which supports dynamic update of
the frequency, we need to configure it at mid frequency of
the vco frequency range and enable it. Update the PLLs
ops for PLLs which support dynamic update of the frequency.

Change-Id: I7686c6525aa4c3d7473e2dece47191daa6ae6935
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent b724dbe3

drivers/clk/qcom/dispcc-sm6150.c

+14 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -139,6 +139,18 @@ static struct alpha_pll_config disp_cc_pll0_config = { 
	.test_ctl_hi_mask = 0x1,

};



static struct clk_init_data disp_cc_pll0_out_main_sa6155 = {

	.name = "disp_cc_pll0_out_main",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_cx,

	.num_rate_max = VDD_NUM,

	.rate_max = (unsigned long[VDD_NUM]) {

		[VDD_MIN] = 1000000000,

		[VDD_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll disp_cc_pll0_out_main = {

	.offset = 0x0,

	.vco_table = disp_cc_pll_vco,
@@ -825,6 +837,7 @@ static void dispcc_sm6150_fixup_sa6155(struct platform_device *pdev) 
{

	vdd_cx.num_levels = VDD_NUM_SA6155;

	vdd_cx.cur_level = VDD_NUM_SA6155;

	disp_cc_pll0_out_main.clkr.hw.init = &disp_cc_pll0_out_main_sa6155;

}



static int disp_cc_sm6150_probe(struct platform_device *pdev)

drivers/clk/qcom/gpucc-sm6150.c

+38 −0
Original line number Diff line number Diff line
@@ -101,6 +101,14 @@ static struct pll_vco gpu_cc_pll_vco[] = { 
	{ 500000000,  1000000000, 2 },

};



static struct pll_vco gpu_cc_pll0_vco[] = {

	{ 1000000000, 2000000000, 0 },

};



static struct pll_vco gpu_cc_pll1_vco[] = {

	{ 500000000,  1000000000, 2 },

};



/* 1020MHz configuration */

static struct alpha_pll_config gpu_pll0_config = {

	.l = 0x35,
@@ -129,6 +137,18 @@ static struct alpha_pll_config gpu_pll1_config = { 
	.aux2_output_mask = BIT(2),

};



static struct clk_init_data gpu_cc_pll0_out_aux2_sa6155 = {

	.name = "gpu_cc_pll0_out_aux2",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_mx,

	.num_rate_max = VDD_MX_NUM,

	.rate_max = (unsigned long[VDD_MX_NUM]) {

		[VDD_MX_MIN] = 1000000000,

		[VDD_MX_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = {

	.offset = 0x0,

	.vco_table = gpu_cc_pll_vco,
@@ -150,6 +170,18 @@ static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { 
	},

};



static struct clk_init_data gpu_cc_pll1_out_aux2_sa6155 = {

	.name = "gpu_cc_pll1_out_aux2",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_mx,

	.num_rate_max = VDD_MX_NUM,

	.rate_max = (unsigned long[VDD_MX_NUM]) {

		[VDD_MX_MIN] = 1000000000,

		[VDD_MX_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = {

	.offset = 0x100,

	.vco_table = gpu_cc_pll_vco,
@@ -567,6 +599,12 @@ static void gpucc_sm6150_fixup_sa6155(struct platform_device *pdev) 
	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_HIGH_L1] = 0;

	gpu_cc_gx_gfx3d_clk_src.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src_sa6155;



	gpu_cc_pll0_out_aux2.vco_table = gpu_cc_pll0_vco;

	gpu_cc_pll0_out_aux2.num_vco = ARRAY_SIZE(gpu_cc_pll0_vco);

	gpu_cc_pll0_out_aux2.clkr.hw.init = &gpu_cc_pll0_out_aux2_sa6155;

	gpu_cc_pll1_out_aux2.vco_table = gpu_cc_pll1_vco;

	gpu_cc_pll1_out_aux2.num_vco = ARRAY_SIZE(gpu_cc_pll1_vco);

	gpu_cc_pll1_out_aux2.clkr.hw.init = &gpu_cc_pll1_out_aux2_sa6155;

	pdev->dev.driver->pm =  &gpu_cc_sm6150_pm_ops;

}

drivers/clk/qcom/videocc-sm6150.c

+13 −0
Original line number Diff line number Diff line
@@ -98,6 +98,18 @@ static struct alpha_pll_config video_pll0_config = { 
	.test_ctl_hi_mask = 0x1,

};



static struct clk_init_data video_pll0_out_main_sa6155 = {

	.name = "video_pll0_out_main",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_cx,

	.num_rate_max = VDD_NUM,

	.rate_max = (unsigned long[VDD_NUM]) {

		[VDD_MIN] = 1000000000,

		[VDD_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll video_pll0_out_main = {

	.offset = 0x42c,

	.vco_table = video_cc_pll_vco,
@@ -358,6 +370,7 @@ static void videocc_sm6150_fixup_sa6155(struct platform_device *pdev) 
	vdd_cx.num_levels = VDD_NUM_SA6155;

	vdd_cx.cur_level = VDD_NUM_SA6155;



	video_pll0_out_main.clkr.hw.init = &video_pll0_out_main_sa6155,

	pdev->dev.driver->pm =  &video_cc_sa6150_pm_ops;

}