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Commit b724dbe3 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

clk: qcom: Add support for dynamic update in slew ops 



Add support for dynamic update PLLs in slew ops and
also reconfigure the PLL in enable or set_rate if it lost
L value and add all trion pll registers for register dumps.

Change-Id: If12c017a199e59d8481b9c183feb45b2c28731af
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent 70266ab9

drivers/clk/qcom/clk-alpha-pll.c

+69 −7
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015, 2017-2020, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -1156,8 +1156,18 @@ static void clk_trion_pll_list_registers(struct seq_file *f, struct clk_hw *hw) 
		{"PLL_L_VAL", 0x4},

		{"PLL_CAL_L_VAL", 0x8},

		{"PLL_USER_CTL", 0xC},

		{"PLL_USER_CTL_U", 0x10},

		{"PLL_USER_CTL_U1", 0x14},

		{"PLL_CONFIG_CTL", 0x18},

		{"PLL_CONFIG_CTL_U", 0x1C},

		{"PLL_CONFIG_CTL_U1", 0x20},

		{"PLL_TEST_CTL", 0x24},

		{"PLL_TEST_CTL_U", 0x28},

		{"PLL_TEST_CTL_U1", 0x2C},

		{"PLL_STATUS", 0x30},

		{"PLL_FREQ_CTL", 0x34},

		{"PLL_OPMODE", 0x38},

		{"PLL_STATE", 0x38},

		{"PLL_ALPHA_VAL", 0x40},

	};
@@ -1767,9 +1777,9 @@ static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate, 
	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long freq_hz;

	const struct pll_vco *curr_vco = NULL, *vco;

	u32 l, ctl;

	u32 l, ctl, l_val;

	u64 a;

	int i = 0;

	int ret, i;



	freq_hz = alpha_pll_round_rate(pll, rate, parent_rate, &l, &a);

	if (freq_hz != rate) {
@@ -1807,6 +1817,27 @@ static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (curr_vco->val != vco->val)

		return clk_alpha_pll_set_rate(hw, rate, parent_rate);



	ret = regmap_read(pll->clkr.regmap, pll->offset + PLL_L_VAL, &l_val);

	if (ret)

		return ret;



	/* PLL has lost it's L value, needs reconfiguration */

	if (!l_val) {

		if (pll->type == AGERA_PLL)

			ret = clk_agera_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		else

			ret = clk_alpha_pll_configure(pll, pll->clkr.regmap,

						pll->config);



		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	a = a << (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);



	regmap_write(pll->clkr.regmap, pll->offset + PLL_L_VAL, l);
@@ -1816,8 +1847,15 @@ static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate, 
	/* Ensure that the write above goes through before proceeding. */

	mb();



	if (clk_hw_is_enabled(hw))

	regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,

			PLL_ALPHA_EN, PLL_ALPHA_EN);



	if (clk_hw_is_enabled(hw)) {

		if (pll->flags & SUPPORTS_DYNAMIC_UPDATE)

			clk_alpha_pll_dynamic_update(pll);

		else

			clk_alpha_pll_slew_update(pll);

	}



	return 0;

}
@@ -1834,7 +1872,7 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw) 
	struct clk_hw *parent;

	const struct pll_vco *vco = NULL;

	u64 a;

	u32 l, ctl;

	u32 l, ctl, l_val;

	int rc, i = 0;



	parent = clk_hw_get_parent(hw);
@@ -1843,6 +1881,26 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw) 
		return -EINVAL;

	}



	rc = regmap_read(pll->clkr.regmap, pll->offset + PLL_L_VAL, &l_val);

	if (rc)

		return rc;



	/* PLL has lost it's L value, needs reconfiguration */

	if (!l_val) {

		if (pll->type == AGERA_PLL)

			rc = clk_agera_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		else

			rc = clk_alpha_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		if (rc) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return rc;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);

	ctl >>= PLL_POST_DIV_SHIFT;

	ctl &= PLL_POST_DIV_MASK;
@@ -1917,6 +1975,9 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw) 
	regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,

				PLL_ALPHA_EN, PLL_ALPHA_EN);



	if (pll->flags & SUPPORTS_DYNAMIC_UPDATE)

		return clk_alpha_pll_dynamic_update(pll);

	else

		return clk_alpha_pll_slew_update(pll);

}
@@ -1934,6 +1995,7 @@ static int clk_alpha_pll_slew_enable(struct clk_hw *hw) 
const struct clk_ops clk_alpha_pll_slew_ops = {

	.enable = clk_alpha_pll_slew_enable,

	.disable = clk_alpha_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_alpha_pll_slew_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_alpha_pll_slew_set_rate,