clk: qcom: clk-alpha-pll: Use a custom recalc_rate callback for Regera PLL

The current generic recalc_rate callback that's being used for
Regera PLLs uses the post-divider settings to derive the current
rate for these PLLs. This makes the PLL rate incorrect since the
divider settings are also considered in the corresponding postdiv
operations.
Add a custom recalc_rate callback for the Regera PLLs to fix this
incoherence.

Change-Id: I2cfdd472b3771ab201f5b1d99b8477357474219a
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>