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Commit c99c7a9a authored by Kelvin Cheung's avatar Kelvin Cheung Committed by Stephen Boyd
Browse files

clk: Loongson1: Update clocks of Loongson1B 



This patch updates some clock names of Loongson1B,
and adds AC97, DMA and NAND clock.

Signed-off-by: default avatarKelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent a8e3ced4

drivers/clk/loongson1/clk-loongson1b.c

+13 −10
Original line number Original line Diff line number Diff line
@@ -37,19 +37,19 @@ static const struct clk_ops ls1x_pll_clk_ops = { 
	.recalc_rate = ls1x_pll_recalc_rate,

	.recalc_rate = ls1x_pll_recalc_rate,

};

};





static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };

static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", };

static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };

static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", };

static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };

static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", };





void __init ls1x_clk_init(void)

void __init ls1x_clk_init(void)

{

{

	struct clk_hw *hw;

	struct clk_hw *hw;





	hw = clk_hw_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);

	hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);

	clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);

	clk_hw_register_clkdev(hw, "osc_clk", NULL);





	/* clock derived from 33 MHz OSC clk */

	/* clock derived from 33 MHz OSC clk */

	hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk",

	hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",

				 &ls1x_pll_clk_ops, 0);

				 &ls1x_pll_clk_ops, 0);

	clk_hw_register_clkdev(hw, "pll_clk", NULL);

	clk_hw_register_clkdev(hw, "pll_clk", NULL);
@@ -104,6 +104,7 @@ void __init ls1x_clk_init(void) 
			       CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,

			       CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,

			       BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);

			       BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);

	clk_hw_register_clkdev(hw, "ahb_clk", NULL);

	clk_hw_register_clkdev(hw, "ahb_clk", NULL);

	clk_hw_register_clkdev(hw, "ls1x-dma", NULL);

	clk_hw_register_clkdev(hw, "stmmaceth", NULL);

	clk_hw_register_clkdev(hw, "stmmaceth", NULL);





	/* clock derived from AHB clk */

	/* clock derived from AHB clk */
@@ -111,9 +112,11 @@ void __init ls1x_clk_init(void) 
	hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,

	hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,

					DIV_APB);

					DIV_APB);

	clk_hw_register_clkdev(hw, "apb_clk", NULL);

	clk_hw_register_clkdev(hw, "apb_clk", NULL);

	clk_hw_register_clkdev(hw, "ls1x_i2c", NULL);

	clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);

	clk_hw_register_clkdev(hw, "ls1x_pwmtimer", NULL);

	clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);

	clk_hw_register_clkdev(hw, "ls1x_spi", NULL);

	clk_hw_register_clkdev(hw, "ls1x-nand", NULL);

	clk_hw_register_clkdev(hw, "ls1x_wdt", NULL);

	clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);

	clk_hw_register_clkdev(hw, "ls1x-spi", NULL);

	clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);

	clk_hw_register_clkdev(hw, "serial8250", NULL);

	clk_hw_register_clkdev(hw, "serial8250", NULL);

}
 
}